arc: Don't generate dynamic relocation for non SEC_ALLOC sections

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 8db29522aa6e981276e7d5dd4ede6e2ff247fa01..5270aeefa80e50cc042a5b89b212f9571a8c7501 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2019 Free Software Foundation, Inc.
+   Copyright (C) 1993-2020 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -392,6 +392,7 @@ decode_mips_operand (const char *p)
 
 /* MIPS Enhanced VA Scheme.  */
 #define EVA    ASE_EVA
+#define EVAR6  ASE_EVA_R6
 
 /* TLB invalidate instruction support.  */
 #define TLBINV ASE_EVA
@@ -665,7 +666,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"aclr",               "\\,~(b)",      0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS,        0,              0,              MC,     0 },
 {"aclr",               "\\,A(b)",      0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              0,              MC,     0 },
 {"add",                        "d,v,t",        0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
-{"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"add",                        "D,S,T",        0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"add.s",              "D,V,T",        0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
@@ -1014,7 +1015,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cvt.pw.ps",          "D,S",          0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              0,              M3D,    0 },
 {"dabs",               "d,v",          0,    (int) M_DABS,     INSN_MACRO,             0,              I3,             0,      0 },
 {"dadd",               "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
-{"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      0 },
 {"dadd",               "D,S,T",        0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"daddi",              "t,r,j",        0x60000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      I69 },
@@ -1172,7 +1173,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsrl",               "D,S,T",        0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsub",               "d,v,t",        0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
-{"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      0 },
 {"dsub",               "D,S,T",        0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsubu",              "d,v,t",        0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
@@ -1954,7 +1955,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ssnop is at the start of the table.  */
 {"standby",            "",             0x42000021, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"sub",                        "d,v,t",        0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
-{"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sub",                        "D,S,T",        0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"sub.d",              "D,V,T",        0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
@@ -2638,6 +2639,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lhe",                        "t,A(b)",       0,    (int) M_LHE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"lle",                        "t,+j(b)",      0x7c00002e, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lle",                        "t,A(b)",       0,    (int) M_LLE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
+{"llwpe",              "t,d,s",        0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM,      0,              0,              EVAR6,  0 },
+{"llwpe",              "t,d,A(b)",     0,    (int) M_LLWPE_AB, INSN_MACRO,             0,              0,              EVAR6,  0 },
 {"lwe",                        "t,+j(b)",      0x7c00002f, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lwe",                        "t,A(b)",       0,    (int) M_LWE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"lwle",               "t,+j(b)",      0x7c000019, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    I37 },
@@ -2648,6 +2651,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sbe",                        "t,A(b)",       0,    (int) M_SBE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"sce",                        "t,+j(b)",      0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM,          0,              0,              EVA,    0 },
 {"sce",                        "t,A(b)",       0,    (int) M_SCE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
+{"scwpe",              "t,d,s",        0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM,     0,              0,              EVAR6,  0 },
+{"scwpe",              "t,d,A(b)",     0,    (int) M_SCWPE_AB, INSN_MACRO,             0,              0,              EVAR6,  0 },
 {"she",                        "t,+j(b)",      0x7c00001d, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
 {"she",                        "t,A(b)",       0,    (int) M_SHE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"swe",                        "t,+j(b)",      0x7c00001f, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
@@ -3266,7 +3271,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* MIPS r6.  */
 {"aui",                        "t,s,u",        0x3c000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
 {"auipc",              "s,u",          0xec1e0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
-{"daui",               "t,s,u",        0x74000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
+{"daui",               "t,-s,u",       0x74000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
 {"dahi",               "s,-d,u",       0x04060000, 0xfc1f0000, MOD_1,                  0,              I69,            0,      0 },
 {"dati",               "s,-d,u",       0x041e0000, 0xfc1f0000, MOD_1,                  0,              I69,            0,      0 },