sh-opc.h (sh_table): Remove ftst/nan.

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 5ca5ef228d4e4e6db7de019703e8d2b81d2d7941..6a04f7c872561c19b635c6d1ce5cbeb3a2ab3285 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -101,6 +101,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 /* end-sanitize-tx49 */               \
                  )
 
+#define G3 (I4             \
+/* start-sanitize-tx49 */  \
+            | T4           \
+/* end-sanitize-tx49 */    \
+            )
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -370,9 +375,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"dmulou",  "d,v,t",   3,    (int) M_DMULOU,   INSN_MACRO      },
 {"dmulou",  "d,v,I",   3,    (int) M_DMULOU_I, INSN_MACRO      },
 {"dmult",   "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,      I3},
+  /* start-sanitize-tx49 */
 {"dmult",   "d,s,t",   0x0000001c, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
+  /* end-sanitize-tx49 */
 {"dmultu",  "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,      I3},
+  /* start-sanitize-tx49 */
 {"dmultu",  "d,s,t",   0x0000001d, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
+  /* end-sanitize-tx49 */
 {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t,      I3      }, /* dsub 0 */
 {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t,      I3      }, /* dsubu 0*/
 {"drem",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
@@ -384,8 +393,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
   /* start-sanitize-vr5400 */
 {"dret",    "",                0x7000003e, 0xffffffff, 0,      N5      },
 {"drorv",   "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5      },
-{"dror32",  "d,t,>",   0x0020003e, 0xffe0003f, WR_d|RD_t,      N5      },
-{"dror",    "d,t,<",   0x00200036, 0xffe0003f, WR_d|RD_t,      N5      },
+{"dror32",  "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,      N5      },
+{"dror",    "d,w,>",   0x0020003e, 0xffe0003f, WR_d|RD_t,      N5      },
+{"dror",    "d,w,<",   0x00200036, 0xffe0003f, WR_d|RD_t,      N5      },
   /* end-sanitize-vr5400 */
 {"dsllv",   "d,t,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3      },
 {"dsll32",  "d,w,<",   0x0000003c, 0xffe0003f, WR_d|RD_t,      I3      },
@@ -782,7 +792,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"pxor",   "d,v,t",    0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
   /* end-sanitize-r5900 */
 
-{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,   I4|T4   },
+{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,           G3      },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,      I4      },
 
   /* start-sanitize-r5900 */
@@ -982,15 +992,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,        N5      },
 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
-{"c.eq.ob", "S,k",     0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"c.eq.ob", "S,T",     0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"c.eq.ob", "S,T[e]",  0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
-{"c.le.ob", "S,k",     0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
+{"c.eq.ob", "S,k",     0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"c.le.ob", "S,T",     0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"c.le.ob", "S,T[e]",  0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
-{"c.lt.ob", "S,k",     0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
+{"c.le.ob", "S,k",     0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"c.lt.ob", "S,T",     0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"c.lt.ob", "S,T[e]",  0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
+{"c.lt.ob", "S,k",     0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,        N5      },
 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
@@ -1000,18 +1010,18 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,        N5      },
 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
-{"mula.ob", "S,k",     0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"mula.ob", "S,T",     0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"mula.ob", "S,T[e]",  0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
-{"mull.ob", "S,k",     0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
+{"mula.ob", "S,k",     0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"mull.ob", "S,T",     0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"mull.ob", "S,T[e]",  0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
-{"muls.ob", "S,k",     0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
+{"mull.ob", "S,k",     0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"muls.ob", "S,T",     0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"muls.ob", "S,T[e]",  0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
-{"mulsl.ob","S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
+{"muls.ob", "S,k",     0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"mulsl.ob","S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"mulsl.ob","S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, N5     },
+{"mulsl.ob","S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5     },
 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,        N5      },
 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
@@ -1027,7 +1037,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"rach.ob", "D",       0x4a00003f, 0xfffff83f, WR_D, N5        },
 {"racl.ob", "D",       0x4800003f, 0xfffff83f, WR_D, N5        },
 {"racm.ob", "D",       0x4900003f, 0xfffff83f, WR_D, N5        },
-{"rzu.ob",  "D,S,k",    0x4bc00020, 0xffe0003f, WR_D|RD_S|RD_T,        N5      },
+{"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,        N5      },
 {"shfl.mixh.ob","D,S,T",0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, N5     },
 {"shfl.mixl.ob","D,S,T",0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, N5     },
 {"shfl.pach.ob","D,S,T",0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, N5     },