Remove unnecessary @w{} in gdb.texinfo

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index feb96a57bf73a6df1dbdc30304e8871591b2489e..6bdf60cd4d7ed262d3a04d254884ab3f73b6141e 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -134,8 +134,8 @@ decode_mips_operand (const char *p)
     case 'S': REG (5, 11, FP);
     case 'T': REG (5, 16, FP);
     case 'U': SPECIAL (10, 11, CLO_CLZ_DEST);
-    case 'V': REG (5, 11, FP);
-    case 'W': REG (5, 16, FP);
+    case 'V': OPTIONAL_REG (5, 11, FP);
+    case 'W': OPTIONAL_REG (5, 16, FP);
     case 'X': REG (5, 6, VEC);
     case 'Y': REG (5, 11, VEC);
     case 'Z': REG (5, 16, VEC);
@@ -153,12 +153,12 @@ decode_mips_operand (const char *p)
     case 'o': SINT (16, 0);
     case 'p': BRANCH (16, 0, 2);
     case 'q': HINT (10, 6);
-    case 'r': REG (5, 21, GP);
+    case 'r': OPTIONAL_REG (5, 21, GP);
     case 's': REG (5, 21, GP);
     case 't': REG (5, 16, GP);
     case 'u': HINT (16, 0);
-    case 'v': REG (5, 21, GP);
-    case 'w': REG (5, 16, GP);
+    case 'v': OPTIONAL_REG (5, 21, GP);
+    case 'w': OPTIONAL_REG (5, 16, GP);
     case 'x': REG (0, 0, GP);
     case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
     }
@@ -921,8 +921,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dctr",               "o(b)",         0xbc050000, 0xfc1f0000, RD_2,                   0,              I3,             0,      0 },
 {"dctw",               "o(b)",         0xbc090000, 0xfc1f0000, RD_2,                   0,              I3,             0,      0 },
 {"deret",              "",             0x4200001f, 0xffffffff, NODS,                   0,              I32|G2,         0,      0 },
-{"dext",               "t,r,I,+I",     0,    (int) M_DEXT,     INSN_MACRO,             0,              I65,            0,      0 },
-{"dext",               "t,r,+A,+C",    0x7c000003, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
+{"dext",               "t,r,+A,+H",    0x7c000003, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
+{"dext",               "t,r,+A,+G",    0x7c000001, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 }, /* dextm */
+{"dext",               "t,r,+E,+H",    0x7c000002, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 }, /* dextu */
 {"dextm",              "t,r,+A,+G",    0x7c000001, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
 {"dextu",              "t,r,+E,+H",    0x7c000002, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
 /* For ddiv, see the comments about div.  */
@@ -936,8 +937,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"di",                 "",             0x42000039, 0xffffffff, WR_C0,                  0,              EE,             0,      0 },
 {"di",                 "",             0x41606000, 0xffffffff, WR_C0,                  0,              I33,            0,      0 },
 {"di",                 "t",            0x41606000, 0xffe0ffff, WR_1|WR_C0,             0,              I33,            0,      0 },
-{"dins",               "t,r,I,+I",     0,    (int) M_DINS,     INSN_MACRO,             0,              I65,            0,      0 },
 {"dins",               "t,r,+A,+B",    0x7c000007, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
+{"dins",               "t,r,+A,+F",    0x7c000005, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 }, /* dinsm */
+{"dins",               "t,r,+E,+F",    0x7c000006, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 }, /* dinsu */
 {"dinsm",              "t,r,+A,+F",    0x7c000005, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
 {"dinsu",              "t,r,+E,+F",    0x7c000006, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
 /* The MIPS assembler treats the div opcode with two operands as