* gas/macros/macros.exp (strings): Update xfails.

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 3212c01c3f65983e07106fcfa8d9d74c44d06c7f..6e8adc5d1923bf7b0e1d7fd971fe630a4d50b67f 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -75,8 +75,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 
 #define IS_M    INSN_MULT
 
-#define        WR_MACC INSN_WRITE_MDMX_ACC
-#define        RD_MACC INSN_READ_MDMX_ACC
+#define WR_MACC INSN_WRITE_MDMX_ACC
+#define RD_MACC INSN_READ_MDMX_ACC
 
 #define I1     INSN_ISA1
 #define I2     INSN_ISA2
@@ -86,11 +86,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I32    INSN_ISA32
 #define I64     INSN_ISA64
 
+/* MIPS64 MIPS-3D ASE support.  */
+#define I16     INSN_MIPS16
+
 /* MIPS64 MIPS-3D ASE support.  */
 #define M3D     INSN_MIPS3D
 
 /* MIPS64 MDMX ASE support.  */
-#define MX     INSN_MDMX
+#define MX      INSN_MDMX
 
 #define P3     INSN_4650
 #define L1     INSN_4010
@@ -477,7 +480,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
 {"divu",    "d,v,t",   0,    (int) M_DIVU_3,   INSN_MACRO,             I1      },
 {"divu",    "d,v,I",   0,    (int) M_DIVU_3I,  INSN_MACRO,             I1      },
-{"dla",     "t,o(b)",  0x64000000, 0xfc000000, WR_t|RD_s,              I3      }, /* daddiu */
 {"dla",     "t,A(b)",  0,    (int) M_DLA_AB,   INSN_MACRO,             I3      },
 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                  I3      }, /* addiu */
 {"dli",            "t,i",      0x34000000, 0xffe00000, WR_t,                   I3      }, /* ori */
@@ -568,10 +570,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"jal",     "a",       0x0c000000, 0xfc000000, UBD|WR_31,              I1      },
-  /* jalx really should only be avaliable if mips16 is available,
-     but for now make it I1. */
-{"jalx",    "a",       0x74000000, 0xfc000000, UBD|WR_31,              I1      },
-{"la",      "t,o(b)",  0x24000000, 0xfc000000, WR_t|RD_s,              I1      }, /* addiu */
+{"jalx",    "a",       0x74000000, 0xfc000000, UBD|WR_31,              I16     },
 {"la",      "t,A(b)",  0,    (int) M_LA_AB,    INSN_MACRO,             I1      },
 {"lb",      "t,o(b)",  0x80000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
 {"lb",      "t,A(b)",  0,    (int) M_LB_AB,    INSN_MACRO,             I1      },
@@ -1007,11 +1006,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ush",     "t,A(b)",  0,    (int) M_USH_A,    INSN_MACRO,             I1      },
 {"usw",     "t,o(b)",  0,    (int) M_USW,      INSN_MACRO,             I1      },
 {"usw",     "t,A(b)",  0,    (int) M_USW_A,    INSN_MACRO,             I1      },
-{"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
-{"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             I1      },
-{"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
-{"xor.qh",  "X,Y,Q",   0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
-{"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,              I1      },
 {"wach.ob", "Y",       0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D,      MX|SB1  },
 {"wach.qh", "Y",       0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D,      MX      },
 {"wacl.ob", "Y,Z",     0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
@@ -1020,6 +1014,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                  I32     },
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,                   L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                L1      },
+{"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
+{"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             I1      },
+{"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
+{"xor.qh",  "X,Y,Q",   0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
+{"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,              I1      },
 
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the