{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32 },
{"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 },
-{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33, 0, 0 },
+{"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 },
{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33, 0, 0 },
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65, 0, 0 },
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65, 0, 0 },
a source and a destination). To get the div machine instruction,
you must use an explicit destination of $0. */
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 },
-{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 },
+{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_t|WR_HILO, 0, I1, 0, 0 },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 },
{"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE, 0, 0 },
-{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, EE, 0, 0 },
+{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_t|WR_HILO, 0, EE, 0, 0 },
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF },
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1, 0, 0 },
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, 0, 0 },
/* For divu, see the comments about div. */
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 },
-{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1, 0, 0 },
+{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_t|WR_HILO, 0, I1, 0, 0 },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 },
{"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE, 0, 0 },
-{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, EE, 0, 0 },
+{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_t|WR_HILO, 0, EE, 0, 0 },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 },
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3, 0, 0 }, /* addiu */
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32, 0 },
{"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 },
-{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33, 0, 0 },
+{"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 },
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33, 0, 0 },
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32, 0 },
assembler, but will never match user input (because the line above
will match first). */
{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 },
-{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1, 0, 0 },
+{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_31, 0, I1, 0, 0 },
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1, 0, 0 },
/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
with the same hazard barrier effect. */
-{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32, 0, 0 },
+{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_31, 0, I32, 0, 0 },
{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32, 0, 0 },
/* SVR4 PIC code requires special handling for jal, so it must be a
macro. */
{"laad", "d,(b),t", 0x700004df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 },
{"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
{"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
-{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 },
-{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 },
-{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 },
-{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 },
+{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
+{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
+{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
+{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
{"las", "d,(b)", 0x7000029f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
{"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2, 0, 0 },
{"law", "d,(b),t", 0x7000059f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2, 0, 0 },
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX, 0 },
{"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, N54, 0, 0 },
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX, 0 },
-{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 },/*nor d,s,0*/
+{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s, 0, I1, 0, 0 },/*nor d,s,0*/
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 },
{"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 },