[ARM] Support for ARMv8.1 Adv.SIMD extension

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 6e0299e25cebcefcfd63b6a181ebc7fc9fea6fa5..a0b0e26988ff1dd3a5fa4284863b03e1b0599224 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2014 Free Software Foundation, Inc.
+   Copyright (C) 1993-2015 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -48,11 +48,11 @@ decode_mips_operand (const char *p)
        case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
        case 's': SPECIAL (5, 21, NON_ZERO_REG);
        case 't': SPECIAL (5, 16, NON_ZERO_REG);
-       case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE);
+       case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
        case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
        case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
        case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
-       case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE);
+       case 'y': PREV_CHECK (5, 21, FALSE, TRUE, FALSE, FALSE);
        case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
        case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
        }
@@ -430,7 +430,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"move",               "d,s",          0x00000025, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* or */
 {"b",                  "p",            0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* beq 0,0 */
 {"b",                  "p",            0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* bgez 0 */
-{"nal",                        "p",            0x04100000, 0xffff0000, WR_31|CBD,              INSN2_ALIAS,    I1,             0,      0 },/* bltzal 0 */
+{"nal",                        "",             0x04100000, 0xffffffff, WR_31|CBD,              INSN2_ALIAS,    I1,             0,      0 },/* bltzal 0 */
 {"bal",                        "p",            0x04110000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS,    I1,             0,      0 },/* bgezal 0*/
 {"bc",                 "+'",           0xc8000000, 0xfc000000, NODS,                   0,              I37,            0,      0 },
 {"balc",               "+'",           0xe8000000, 0xfc000000, WR_31|NODS,             0,              I37,            0,      0 },
@@ -1147,6 +1147,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsubu",              "d,v,I",        0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"dvpe",               "",             0x41600001, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"dvpe",               "t",            0x41600001, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
+{"dvp",                        "",             0x41600024, 0xffffffff, TRAP,                   0,              I37,            0,      0 },
+{"dvp",                        "t",            0x41600024, 0xffe0ffff, WR_1|TRAP,              0,              I37,            0,      0 },
 {"ei",                 "",             0x42000038, 0xffffffff, WR_C0,                  0,              EE,             0,      0 },
 {"ei",                 "",             0x41606020, 0xffffffff, WR_C0,                  0,              I33,            0,      0 },
 {"ei",                 "t",            0x41606020, 0xffe0ffff, WR_1|WR_C0,             0,              I33,            0,      0 },
@@ -1156,6 +1158,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"eretnc",             "",             0x42000058, 0xffffffff, NODS,                   0,              I36,            0,      0 },
 {"evpe",               "",             0x41600021, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"evpe",               "t",            0x41600021, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
+{"evp",                        "",             0x41600004, 0xffffffff, TRAP,                   0,              I37,            0,      0 },
+{"evp",                        "t",            0x41600004, 0xffe0ffff, WR_1|TRAP,              0,              I37,            0,      0 },
 {"ext",                        "t,r,+A,+C",    0x7c000000, 0xfc00003f, WR_1|RD_2,              0,              I33,            0,      0 },
 {"exts32",             "t,r,+p,+s",    0x7000003b, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"exts",               "t,r,+P,+S",    0x7000003b, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 }, /* exts32 */
@@ -3254,6 +3258,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"jic",                        "t,j",          0xd8000000, 0xffe00000, RD_1|NODS,              0,              I37,            0,      0 },
 
 {"bnezc",              "-s,+\"",       0xf8000000, 0xfc000000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"jalrc",              "t",            0xf8000000, 0xffe0ffff, RD_1|NODS,              0,              I37,            0,      0 },
 {"jialc",              "t,j",          0xf8000000, 0xffe00000, RD_1|NODS,              0,              I37,            0,      0 },
 
 {"cmp.af.s",           "D,S,T",        0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },