MIPS16/opcodes: Correct 64-bit macros' ISA membership

[deliverable/binutils-gdb.git] / opcodes / mips16-opc.c

diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 14d82bfe8bbc73bb3a80ec80074fb85db37f5936..0c4bb7f53d2f06304686dbc8e064c4d270f73a33 100644 (file)
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -241,9 +241,9 @@ const struct mips_opcode mips16_opcodes[] =
 {"daddu",   "y,P,W",   0xfe00, 0xff00,         WR_1,                   RD_PC,          I3,     0,      0 },
 {"daddu",   "y,S,W",   0xff00, 0xff00,         WR_1,                   RD_SP,          I3,     0,      0 },
 {"ddiv",    "0,x,y",   0xe81e, 0xf81f,         RD_2|RD_3|WR_HI|WR_LO,  0,              I3,     0,      0 },
-{"ddiv",    "z,v,y",   0, (int) M_DDIV_3,      INSN_MACRO,             0,              I1,     0,      0 },
+{"ddiv",    "z,v,y",   0, (int) M_DDIV_3,      INSN_MACRO,             0,              I3,     0,      0 },
 {"ddivu",   "0,x,y",   0xe81f, 0xf81f,         RD_2|RD_3|WR_HI|WR_LO,  0,              I3,     0,      0 },
-{"ddivu",   "z,v,y",   0, (int) M_DDIVU_3,     INSN_MACRO,             0,              I1,     0,      0 },
+{"ddivu",   "z,v,y",   0, (int) M_DDIVU_3,     INSN_MACRO,             0,              I3,     0,      0 },
 {"div",     "0,x,y",   0xe81a, 0xf81f,         RD_2|RD_3|WR_HI|WR_LO,  0,              I1,     0,      0 },
 {"div",     "z,v,y",   0, (int) M_DIV_3,       INSN_MACRO,             0,              I1,     0,      0 },
 {"divu",    "0,x,y",   0xe81b, 0xf81f,         RD_2|RD_3|WR_HI|WR_LO,  0,              I1,     0,      0 },
@@ -252,9 +252,9 @@ const struct mips_opcode mips16_opcodes[] =
 {"dmult",   "x,y",     0xe81c, 0xf81f,         RD_1|RD_2|WR_HI|WR_LO,  0,              I3,     0,      0 },
 {"dmultu",  "x,y",     0xe81d, 0xf81f,         RD_1|RD_2|WR_HI|WR_LO,  0,              I3,     0,      0 },
 {"drem",    "0,x,y",   0xe81e, 0xf81f,         RD_2|RD_3|WR_HI|WR_LO,  0,              I3,     0,      0 },
-{"drem",    "z,v,y",   0, (int) M_DREM_3,      INSN_MACRO,             0,              I1,     0,      0 },
+{"drem",    "z,v,y",   0, (int) M_DREM_3,      INSN_MACRO,             0,              I3,     0,      0 },
 {"dremu",   "0,x,y",   0xe81f, 0xf81f,         RD_2|RD_3|WR_HI|WR_LO,  0,              I3,     0,      0 },
-{"dremu",   "z,v,y",   0, (int) M_DREMU_3,     INSN_MACRO,             0,              I1,     0,      0 },
+{"dremu",   "z,v,y",   0, (int) M_DREMU_3,     INSN_MACRO,             0,              I3,     0,      0 },
 {"dsllv",   "y,x",     0xe814, 0xf81f,         MOD_1|RD_2,     0,              I3,     0,      0 },
 {"dsll",    "x,w,[",   0x3001, 0xf803,         WR_1|RD_2,              0,              I3,     0,      0 },
 {"dsll",    "y,x",     0xe814, 0xf81f,         MOD_1|RD_2,     0,              I3,     0,      0 },
@@ -265,8 +265,8 @@ const struct mips_opcode mips16_opcodes[] =
 {"dsrl",    "y,]",     0xe808, 0xf81f,         MOD_1,                  0,              I3,     0,      0 },
 {"dsrl",    "y,x",     0xe816, 0xf81f,         MOD_1|RD_2,     0,              I3,     0,      0 },
 {"dsubu",   "z,v,y",   0xe002, 0xf803,         WR_1|RD_2|RD_3,         0,              I3,     0,      0 },
-{"dsubu",   "y,x,I",   0, (int) M_DSUBU_I,     INSN_MACRO,             0,              I1,     0,      0 },
-{"dsubu",   "y,I",     0, (int) M_DSUBU_I_2,   INSN_MACRO,             0,              I1,     0,      0 },
+{"dsubu",   "y,x,I",   0, (int) M_DSUBU_I,     INSN_MACRO,             0,              I3,     0,      0 },
+{"dsubu",   "y,I",     0, (int) M_DSUBU_I_2,   INSN_MACRO,             0,              I3,     0,      0 },
 {"exit",    "L",       0xed09, 0xff1f,         TRAP,                   0,              I1,     0,      0 },
 {"exit",    "L",       0xee09, 0xff1f,         TRAP,                   0,              I1,     0,      0 },
 {"exit",    "",                0xef09, 0xffff,         TRAP,                   0,              I1,     0,      0 },