* cris-dis.c (bytes_to_skip): Handle new parameter prefix_matchedp.

[deliverable/binutils-gdb.git] / opcodes / ms1-desc.h

diff --git a/opcodes/ms1-desc.h b/opcodes/ms1-desc.h
index 4a3dd2f5e21105364e46a58293347912e5516ed8..909b32388af91eaecaaab2e9673c5bdcf564442c 100644 (file)
--- a/opcodes/ms1-desc.h
+++ b/opcodes/ms1-desc.h
@@ -40,6 +40,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Selected cpu families.  */
 #define HAVE_CPU_MS1BF
 #define HAVE_CPU_MS1_003BF
+#define HAVE_CPU_MS2BF
 
 #define CGEN_INSN_LSB0_P 1
 
@@ -76,9 +77,9 @@ typedef enum insn_opc {
  , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
  , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
  , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
- , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LDW = 32, OPC_STW = 33
- , OPC_EI = 48, OPC_DI = 49, OPC_SI = 50, OPC_RETI = 51
- , OPC_BREAK = 52, OPC_IFLUSH = 53
+ , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32
+ , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50
+ , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53
 } INSN_OPC;
 
 /* Enum declaration for msopc enums.  */
@@ -107,7 +108,8 @@ typedef enum msys_syms {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MAX
+  MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2
+ , MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -148,20 +150,22 @@ typedef enum ifield_type {
  , MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2
  , MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S
  , MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12
- , MS1_F_UU16, MS1_F_MSOPC, MS1_F_UU_26_25, MS1_F_MASK
- , MS1_F_BANKADDR, MS1_F_RDA, MS1_F_UU_2_25, MS1_F_RBBC
- , MS1_F_PERM, MS1_F_MODE, MS1_F_UU_1_24, MS1_F_WR
- , MS1_F_FBINCR, MS1_F_UU_2_23, MS1_F_XMODE, MS1_F_A23
- , MS1_F_MASK1, MS1_F_CR, MS1_F_TYPE, MS1_F_INCAMT
- , MS1_F_CBS, MS1_F_UU_1_19, MS1_F_BALL, MS1_F_COLNUM
- , MS1_F_BRC, MS1_F_INCR, MS1_F_FBDISP, MS1_F_UU_4_15
- , MS1_F_LENGTH, MS1_F_UU_1_15, MS1_F_RC, MS1_F_RCNUM
- , MS1_F_ROWNUM, MS1_F_CBX, MS1_F_ID, MS1_F_SIZE
- , MS1_F_ROWNUM1, MS1_F_UU_3_11, MS1_F_RC1, MS1_F_CCB
- , MS1_F_CBRB, MS1_F_CDB, MS1_F_ROWNUM2, MS1_F_CELL
- , MS1_F_UU_3_9, MS1_F_CONTNUM, MS1_F_UU_1_6, MS1_F_DUP
- , MS1_F_RC2, MS1_F_CTXDISP, MS1_F_MSYSFRSR2, MS1_F_BRC2
- , MS1_F_BALL2, MS1_F_MAX
+ , MS1_F_UU8, MS1_F_UU16, MS1_F_UU1, MS1_F_MSOPC
+ , MS1_F_UU_26_25, MS1_F_MASK, MS1_F_BANKADDR, MS1_F_RDA
+ , MS1_F_UU_2_25, MS1_F_RBBC, MS1_F_PERM, MS1_F_MODE
+ , MS1_F_UU_1_24, MS1_F_WR, MS1_F_FBINCR, MS1_F_UU_2_23
+ , MS1_F_XMODE, MS1_F_A23, MS1_F_MASK1, MS1_F_CR
+ , MS1_F_TYPE, MS1_F_INCAMT, MS1_F_CBS, MS1_F_UU_1_19
+ , MS1_F_BALL, MS1_F_COLNUM, MS1_F_BRC, MS1_F_INCR
+ , MS1_F_FBDISP, MS1_F_UU_4_15, MS1_F_LENGTH, MS1_F_UU_1_15
+ , MS1_F_RC, MS1_F_RCNUM, MS1_F_ROWNUM, MS1_F_CBX
+ , MS1_F_ID, MS1_F_SIZE, MS1_F_ROWNUM1, MS1_F_UU_3_11
+ , MS1_F_RC1, MS1_F_CCB, MS1_F_CBRB, MS1_F_CDB
+ , MS1_F_ROWNUM2, MS1_F_CELL, MS1_F_UU_3_9, MS1_F_CONTNUM
+ , MS1_F_UU_1_6, MS1_F_DUP, MS1_F_RC2, MS1_F_CTXDISP
+ , MS1_F_IMM16L, MS1_F_LOOPO, MS1_F_CB1SEL, MS1_F_CB2SEL
+ , MS1_F_CB1INCR, MS1_F_CB2INCR, MS1_F_RC3, MS1_F_MSYSFRSR2
+ , MS1_F_BRC2, MS1_F_BALL2, MS1_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) MS1_F_MAX)
@@ -229,11 +233,12 @@ typedef enum cgen_operand_type {
  , MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR
  , MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB
  , MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR
- , MS1_OPERAND_MAX
+ , MS1_OPERAND_LOOPSIZE, MS1_OPERAND_IMM16L, MS1_OPERAND_RC3, MS1_OPERAND_CB1SEL
+ , MS1_OPERAND_CB2SEL, MS1_OPERAND_CB1INCR, MS1_OPERAND_CB2INCR, MS1_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 48
+#define MAX_OPERANDS 55
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8
@@ -245,9 +250,10 @@ typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
- , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_USES_FRDR
- , CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD
+ , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2
+ , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
+ , CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn_attr.  */
@@ -270,6 +276,7 @@ typedef enum cgen_insn_attr {
 #define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0)
 #define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0)
 #define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_JAL_HAZARD)) != 0)
 #define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0)
 #define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
 #define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0)