RISC-V: Add compressed instruction hints, and a few misc cleanups.

[deliverable/binutils-gdb.git] / opcodes / mt-dis.c

diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c
index f72d5b3a87beb3ad0d4487c2268b675d0593edb9..ca67ce298d982a8c11bf4eb95b7d20d80c60d85a 100644 (file)
--- a/opcodes/mt-dis.c
+++ b/opcodes/mt-dis.c
@@ -1,10 +1,11 @@
+/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright (C) 1996-2015 Free Software Foundation, Inc.
+   Copyright (C) 1996-2017 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
 
@@ -28,7 +29,7 @@
 #include "sysdep.h"
 #include <stdio.h>
 #include "ansidecl.h"
-#include "dis-asm.h"
+#include "disassemble.h"
 #include "bfd.h"
 #include "symcat.h"
 #include "libiberty.h"