THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2010 Free Software Foundation, Inc.
+Copyright (C) 1996-2015 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
{ "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-uimm16", HW_H_UIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
{ OR1K_F_RESV_25_10, "f-resv-25-10", 0, 32, 25, 10, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_25_5, "f-resv-25-5", 0, 32, 25, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_23_8, "f-resv-23-8", 0, 32, 23, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { OR1K_F_RESV_20_21, "f-resv-20-21", 0, 32, 20, 21, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_20_5, "f-resv-20-5", 0, 32, 20, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_20_4, "f-resv-20-4", 0, 32, 20, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ OR1K_F_RESV_15_8, "f-resv-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{
/* pc: program counter */
{ "pc", OR1K_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sys-sr: supervision register */
{ "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-esr0: exception supervision register 0 */
{ "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-epcr0: exception PC register 0 */
{ "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-lee: SR little endian enable bit */
{ "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-f: SR flag bit */
{ "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-cy: SR carry bit */
{ "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-ov: SR overflow bit */
{ "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-ove: SR overflow exception enable bit */
{ "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */
{ "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-cpucfgr-nd: CPUCFGR no delay bit */
{ "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-fpcsr-rm: floating point round mode */
{ "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* mac-machi: MAC HI result register */
{ "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* mac-maclo: MAC LO result register */
{ "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+/* atomic-reserve: atomic reserve flag */
+ { "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+/* atomic-address: atomic address */
+ { "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* uimm6: uimm6 */
{ "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rD: destination register */
{ "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5,
OR1K_INSN_L_SYS, "l-sys", "l.sys", 32,
{ 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* l.msync */
+ {
+ OR1K_INSN_L_MSYNC, "l-msync", "l.msync", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* l.psync */
+ {
+ OR1K_INSN_L_PSYNC, "l-psync", "l.psync", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
+/* l.csync */
+ {
+ OR1K_INSN_L_CSYNC, "l-csync", "l.csync", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
/* l.rfe */
{
OR1K_INSN_L_RFE, "l-rfe", "l.rfe", 32,
OR1K_INSN_L_LWS, "l-lws", "l.lws", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* l.lwa $rD,${simm16}($rA) */
+ {
+ OR1K_INSN_L_LWA, "l-lwa", "l.lwa", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
/* l.lbz $rD,${simm16}($rA) */
{
OR1K_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
OR1K_INSN_L_SH, "l-sh", "l.sh", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* l.swa ${simm16-split}($rA),$rB */
+ {
+ OR1K_INSN_L_SWA, "l-swa", "l.swa", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
/* l.sll $rD,$rA,$rB */
{
OR1K_INSN_L_SLL, "l-sll", "l.sll", 32,