* config/tc-z8k.c (parse_reg): Invalid registers generate an error

[deliverable/binutils-gdb.git] / opcodes / ppc-dis.c

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 372e9b03c009154548ee65e7a96591c2bac1f37c..3df7dc16b06ad618d5ff0e0d436551c83141217b 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -1,5 +1,5 @@
 /* ppc-dis.c -- Disassemble PowerPC instructions
-   Copyright 1994, 1995, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2001, 2002 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -52,8 +52,35 @@ powerpc_dialect(info)
          || strcmp (info->disassembler_options, "booke32") == 0
          || strcmp (info->disassembler_options, "booke64") == 0))
     dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
-  else 
-    dialect |= PPC_OPCODE_403 | PPC_OPCODE_601;
+  else
+    if ((info->mach == bfd_mach_ppc_e500)
+       || (info->disassembler_options
+       && (   strcmp (info->disassembler_options, "e500") == 0
+           || strcmp (info->disassembler_options, "e500x2") == 0)))
+      {
+       dialect |= PPC_OPCODE_BOOKE
+         | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
+         | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+         | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
+         | PPC_OPCODE_RFMCI;
+       /* efs* and AltiVec conflict.  */
+       dialect &= ~PPC_OPCODE_ALTIVEC;
+      }
+  else
+    if (info->disassembler_options
+       && (strcmp (info->disassembler_options, "efs") == 0))
+      {
+       dialect |= PPC_OPCODE_EFS;
+       /* efs* and AltiVec conflict.  */
+       dialect &= ~PPC_OPCODE_ALTIVEC;
+      }
+  else
+    dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
+               | PPC_OPCODE_COMMON);
+
+  if (info->disassembler_options
+      && strcmp (info->disassembler_options, "power4") == 0)
+    dialect |= PPC_OPCODE_POWER4;
 
   if (info->disassembler_options)
     {
@@ -149,6 +176,9 @@ print_insn_powerpc (memaddr, info, bigendian, dialect)
          || (opcode->flags & dialect) == 0)
        continue;
 
+      if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC))
+       continue;
+
       /* Make two passes over the operands.  First see if any of them
         have extraction functions, and, if they do, make sure the
         instruction is valid.  */
@@ -232,14 +262,9 @@ print_insn_powerpc (memaddr, info, bigendian, dialect)
 
                  cr = value >> 2;
                  if (cr != 0)
-                   (*info->fprintf_func) (info->stream, "4*cr%d", cr);
+                   (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
                  cc = value & 3;
-                 if (cc != 0)
-                   {
-                     if (cr != 0)
-                       (*info->fprintf_func) (info->stream, "+");
-                     (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
-                   }
+                 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
                }
            }
 
@@ -267,3 +292,18 @@ print_insn_powerpc (memaddr, info, bigendian, dialect)
 
   return 4;
 }
+
+void
+print_ppc_disassembler_options (FILE * stream)
+{
+  fprintf (stream, "\n\
+The following PPC specific disassembler options are supported for use with\n\
+the -M switch:\n");
+
+  fprintf (stream, "  booke|booke32|booke64    Disassemble the BookE instructions\n");
+  fprintf (stream, "  e500|e500x2              Disassemble the e500 instructions\n");
+  fprintf (stream, "  efs                      Disassemble the EFS instructions\n");
+  fprintf (stream, "  power4                   Disassemble the Power4 instructions\n");
+  fprintf (stream, "  32                       Do not disassemble 64-bit instructions\n");
+  fprintf (stream, "  64                       Allow disassembly of 64-bit instructions\n");
+}