static long extract_sprg (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
static long extract_tbr (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
\f
/* The operands table.
#define D CT + 1
{ 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
- /* The DE field in a DE form instruction. This is like D, but is 12
- bits only. */
-#define DE D + 1
- { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
- /* The DES field in a DES form instruction. This is like DS, but is 14
- bits only (12 stored.) */
-#define DES DE + 1
- { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
/* The DQ field in a DQ form instruction. This is like D, but the
lower four bits are forced to zero. */
-#define DQ DES + 1
+#define DQ D + 1
{ 0xfff0, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
/* The L field in an mtfsf or XFL form instruction. */
#define XFL_L EH + 1
{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
+
+ /* Xilinx APU related masks and macros */
+#define FCRT XFL_L + 1
+#define FCRT_MASK (0x1f << 21)
+ { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
+
+ /* Xilinx FSL related masks and macros */
+#define FSL FCRT + 1
+#define FSL_MASK (0x1f << 11)
+ { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
+
+ /* Xilinx UDI related masks and macros */
+#define URT FSL + 1
+ { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
+
+#define URA URT + 1
+ { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
+
+#define URB URA + 1
+ { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
+
+#define URC URB + 1
+ { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
+
+ /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
+#define XS6 URC + 1
+#define XT6 XS6
+ { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
+
+ /* The XA field in an XX3 form instruction. This is split. */
+#define XA6 XT6 + 1
+ { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
+
+ /* The XB field in an XX3 form instruction. This is split. */
+#define XB6 XA6 + 1
+ { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
+
+ /* The XB field in an XX3 form instruction when it must be the same as
+ the XA field in the instruction. This is used in extended mnemonics
+ like xvmovdp. This is split. */
+#define XB6S XB6 + 1
+ { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
+
+ /* The DM field in an XX3 form instruction. */
+#define DM XB6S + 1
+ { 0x3, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
ppc_cpu_t dialect,
const char **errmsg)
{
- /* This check uses PPC_OPCODE_403 because PPC405 is later defined
- as a synonym. If ever a 405 specific dialect is added this
- check should use that instead. */
if (value > 7
|| (value > 3
- && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
+ && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
*errmsg = _("invalid sprg number");
/* If this is mfsprg4..7 then use spr 260..263 which can be read in
/* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
If not BOOKE or 405, then both use only 272..275. */
- if (val <= 3
- || (val < 0x10 && (insn & 0x100) != 0)
- || (val - 0x10 > 3
- && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
+ if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
+ || (val - 0x10 > 7 && (insn & 0x100) != 0)
+ || val <= 3
+ || (val & 8) != 0)
*invalid = 1;
return val & 7;
}
ret = 0;
return ret;
}
+
+/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
+
+static unsigned long
+insert_xt6 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
+}
+
+static long
+extract_xt6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
+}
+
+/* The XA field in an XX3 form instruction. This is split. */
+
+static unsigned long
+insert_xa6 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
+}
+
+static long
+extract_xa6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
+}
+
+/* The XB field in an XX3 form instruction. This is split. */
+
+static unsigned long
+insert_xb6 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
+}
+
+static long
+extract_xb6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
+}
+
+/* The XB field in an XX3 form instruction when it must be the same as
+ the XA field in the instruction. This is used for extended
+ mnemonics like xvmovdp. This operand is marked FAKE. The insertion
+ function just copies the XA field into the XB field, and the
+ extraction function just checks that the fields are the same. */
+
+static unsigned long
+insert_xb6s (unsigned long insn,
+ long value ATTRIBUTE_UNUSED,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
+}
+
+static long
+extract_xb6s (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
+ || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
+ *invalid = 1;
+ return 0;
+}
\f
/* Macros used to form opcodes. */
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
#define DS_MASK DSO (0x3f, 3)
-/* A DE form instruction. */
-#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
-#define DE_MASK DEO (0x3e, 0xf)
-
/* An EVSEL form instruction. */
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
#define EVSEL_MASK EVSEL(0x3f, 0xff)
/* An X form instruction. */
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+/* An XX3 form instruction. */
+#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
+
+#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
+ | ((((unsigned long)(dm)) & 0x3) << 8))
+
/* A Z form instruction. */
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
/* The mask for an X form instruction. */
#define X_MASK XRC (0x3f, 0x3ff, 1)
+/* The mask for an XX1 form instruction. */
+#define XX1_MASK X (0x3f, 0x3ff)
+
+/* The mask for an XX3 form instruction. */
+#define XX3_MASK XX3 (0x3f, 0xff)
+
+/* The mask for an XX3 form instruction with the DM bits specified. */
+#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
+
/* The mask for a Z form instruction. */
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
#define Z2_MASK ZRC (0x3f, 0xff, 1)
/* The mask for a G form instruction. rc not supported at present. */
#define XW_MASK XW (0x3f, 0x3f, 0)
+/* An APU form instruction. */
+#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
+
+/* The mask for an APU form instruction. */
+#define APU_MASK APU (0x3f, 0x3ff, 1)
+#define APU_RT_MASK (APU_MASK | RT_MASK)
+#define APU_RA_MASK (APU_MASK | RA_MASK)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
#define PPC403 PPC_OPCODE_403
-#define PPC405 PPC403
+#define PPC405 PPC_OPCODE_405
#define PPC440 PPC_OPCODE_440
#define PPC464 PPC440
#define PPC750 PPC
#define PPC860 PPC
#define PPCPS PPC_OPCODE_PPCPS
#define PPCVEC PPC_OPCODE_ALTIVEC
+#define PPCVSX PPC_OPCODE_VSX
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define MFDEC1 PPC_OPCODE_POWER
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
#define BOOKE PPC_OPCODE_BOOKE
-#define BOOKE64 PPC_OPCODE_BOOKE64
#define CLASSIC PPC_OPCODE_CLASSIC
#define PPCE300 PPC_OPCODE_E300
#define PPCSPE PPC_OPCODE_SPE
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR PPC_OPCODE_PMR
#define PPCCHLK PPC_OPCODE_CACHELCK
-#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI PPC_OPCODE_RFMCI
#define E500MC PPC_OPCODE_E500MC
\f
{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}},
+{"get", APU(4, 268,0), APU_RA_MASK, PPC405, {RT, FSL}},
{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, {RT, FSL}},
{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}},
{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}},
{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}},
+{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, {RT, FSL}},
{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}},
+{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, {RT, FSL}},
{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}},
{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}},
{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}},
{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}},
+{"put", APU(4, 332,0), APU_RT_MASK, PPC405, {RA, FSL}},
{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}},
{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, {RA, FSL}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}},
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}},
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}},
{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}},
+{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, {RA, FSL}},
{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}},
{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}},
{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}},
{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}},
{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}},
{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}},
+{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, {RA, FSL}},
{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}},
{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}},
{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}},
{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}},
{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}},
{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}},
{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}},
{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
+{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}},
{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}},
{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, {URT, URA, URB}},
{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}},
{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}},
{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, {URT, URA, URB}},
{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, {URT, URA, URB}},
{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, {URT, URA, URB}},
{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, {URT, URA, URB}},
{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}},
{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, {URT, URA, URB}},
{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, {URT, URA, URB}},
{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}},
{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, {URT, URA, URB}},
+{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, {URT, URA, URB}},
{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}},
-{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}},
-{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}},
-{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}},
-{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}},
-
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}},
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}},
{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}},
{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}},
-{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}},
-{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}},
-
{"rfid", XL(19,18), 0xffffffff, PPC64, {0}},
{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}},
{"rfdi", XL(19,39), 0xffffffff, E500MC, {0}},
{"rfi", XL(19,50), 0xffffffff, COM, {0}},
-{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE, {0}},
+{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}},
{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}},
{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}},
-{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}},
-{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}},
-
{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}},
-{"be", B(22,0,0), B_MASK, BOOKE64, {LI}},
-{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}},
{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}},
-{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}},
-{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}},
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}},
{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}},
{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}},
-
-{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}},
-
-{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}},
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}},
{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}},
{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}},
{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}},
-{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
-
{"wait", X(31,62), 0xffffffff, E500MC, {0}},
-{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}},
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}},
{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}},
{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}},
+{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}},
{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}},
{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}},
-{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}},
-
-{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}},
{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}},
{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}},
{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}},
-{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}},
-
-{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}},
{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}},
{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}},
+{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
-{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, {CT, RA, RB}},
{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}},
{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}},
{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}},
-{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
-
-{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}},
{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}},
{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
+{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}},
-{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"dcbtlse", X(31,174), X_MASK, PPCCHLK, {CT, RA, RB}},
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}},
{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}},
-{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
+{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}},
{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}},
{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}},
-{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}},
{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}},
{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}},
+{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}},
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}},
-{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"icblce", X(31,238), X_MASK, PPCCHLK, {CT, RA, RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}},
{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}},
{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}},
-{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}},
-
-{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}},
{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}},
{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
+{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}},
{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}},
{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}},
{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}},
-{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}},
-
-{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}},
{"mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}},
{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}},
{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}},
-{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}},
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}},
{"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}},
{"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}},
-{"mfpmr", X(31,334), X_MASK, PPCPMR, {RT, PMR}},
+{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}},
{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}},
{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}},
{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}},
-{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}},
-
{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}},
{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}},
{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}},
-{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}},
{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}},
+{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}},
-{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
-{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
-{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"dcblce", X(31,398), X_MASK, PPCCHLK, {CT, RA, RB}},
{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}},
{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}},
{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}},
-{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}},
{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}},
{"mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}},
{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}},
{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}},
-{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}},
{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}},
{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}},
{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}},
-{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}},
-{"mtpmr", X(31,462), X_MASK, PPCPMR, {PMR, RS}},
+{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}},
{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}},
{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}},
{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}},
{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}},
-{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}},
-
{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}},
{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}},
{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}},
{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}},
-{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}},
{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}},
{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}},
{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}},
-{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"icbtlse", X(31,494), X_MASK, PPCCHLK, {CT, RA, RB}},
{"slbia", X(31,498), 0xffffffff, PPC64, {0}},
{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}},
-{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}},
-
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}},
{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}},
{"bblels", X(31,518), X_MASK, PPCBRLK, {0}},
{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
+{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}},
{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}},
-{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}},
-
-{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}},
-
-{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
-
{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}},
{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
+{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}},
{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}},
-{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}},
-
{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}},
+{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}},
+
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}},
{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}},
{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}},
-{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}},
{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}},
{"lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}},
+{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, {FCRT, RA, RB}},
+
{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}},
{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}},
{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}},
-{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}},
-
{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
+{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}},
{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}},
-{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}},
-
-{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}},
-
{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}},
{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
+{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}},
{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}},
{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}},
-{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}},
-
{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}},
+{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}},
+
{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}},
{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}},
{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}},
{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}},
-{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}},
{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}},
{"stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}},
+{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, {FCRT, RA, RB}},
+
{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}},
{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}},
{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}},
{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}},
-{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}},
-
-{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}},
-
{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
+{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}},
{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}},
{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}},
-{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}},
{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}},
{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}},
{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}},
{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}},
{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}},
-{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}},
-
-{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}},
-
{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}},
{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}},
{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
-{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
+
+{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}},
{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}},
{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
+{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}},
+
{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
-
-{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
-{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
+{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}},
{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
-{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}},
-{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}},
{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}},
{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}},
{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}},
{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}},
-{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}},
-
-{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}},
-
{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}},
{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}},
{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}},
-{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}},
-{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
+{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}},
+
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}},
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}},
{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}},
-{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}},
+{"extsw", XRC(31,986,0), XRB_MASK, PPC64, {RA, RS}},
{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}},
-{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}},
-{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}},
-
{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}},
{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
-{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}},
{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}},
{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
+{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}},
+
{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}},
{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}},
{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
-{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}},
{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}},
-{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}},
-{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}},
-{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}},
-{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}},
-{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}},
-{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}},
-
{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}},
{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}},
{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}},
{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}},
{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
+
+{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
+{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
+{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}},
+{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}},
+{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
+
{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}},
{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}},
-{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}},
-{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}},
-{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}},
-{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}},
-{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}},
-{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}},
-{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}},
-{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}},
-{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}},
-{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}},
-{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}},
-{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}},
-
{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}},
{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}},
{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}},
projects / deliverable / binutils-gdb.git / blobdiff