[cpu]

[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index adefd94786def9429720ea2c56b370fe42aff0f2..8e7c1347046d36eb969f7819bdd088aa9e8de5a8 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this file; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -304,10 +304,14 @@ const struct powerpc_operand powerpc_operands[] =
 #define L FXM4 + 1
   { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
-  /* The LEV field in a POWER SC form instruction.  */
-#define LEV L + 1
+  /* The LEV field in a POWER SVC form instruction.  */
+#define SVC_LEV L + 1
   { 7, 5, NULL, NULL, 0 },
 
+  /* The LEV field in an SC form instruction.  */
+#define LEV SVC_LEV + 1
+  { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
   /* The LI field in an I form instruction.  The lower two bits are
      forced to zero.  */
 #define LI LEV + 1
@@ -1818,6 +1822,7 @@ extract_tbr (unsigned long insn,
 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
 #define POWER4 PPC_OPCODE_POWER4
+#define POWER5 PPC_OPCODE_POWER5
 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
 #define PPC403 PPC_OPCODE_403
@@ -1839,6 +1844,7 @@ extract_tbr (unsigned long insn,
 #define BOOKE  PPC_OPCODE_BOOKE
 #define BOOKE64        PPC_OPCODE_BOOKE64
 #define CLASSIC        PPC_OPCODE_CLASSIC
+#define PPCE300 PPC_OPCODE_E300
 #define PPCSPE PPC_OPCODE_SPE
 #define PPCISEL        PPC_OPCODE_ISEL
 #define PPCEFS PPC_OPCODE_EFS
@@ -2749,9 +2755,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bcla+",   B(16,1,1),        B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
 { "bcla",    B(16,1,1),        B_MASK,         COM,            { BO, BI, BDA } },
 
-{ "sc",      SC(17,1,0), 0xffffffff,   PPC,            { 0 } },
-{ "svc",     SC(17,0,0), SC_MASK,      POWER,          { LEV, FL1, FL2 } },
-{ "svcl",    SC(17,0,1), SC_MASK,      POWER,          { LEV, FL1, FL2 } },
+{ "sc",      SC(17,1,0), SC_MASK,      PPC,            { LEV } },
+{ "svc",     SC(17,0,0), SC_MASK,      POWER,          { SVC_LEV, FL1, FL2 } },
+{ "svcl",    SC(17,0,1), SC_MASK,      POWER,          { SVC_LEV, FL1, FL2 } },
 { "svca",    SC(17,1,0), SC_MASK,      PWRCOM,         { SV } },
 { "svcla",   SC(17,1,1), SC_MASK,      POWER,          { SV } },
 
@@ -3008,6 +3014,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "crand",   XL(19,257), XL_MASK,      COM,            { BT, BA, BB } },
 
+{ "hrfid",   XL(19,274), 0xffffffff,   POWER5,         { 0 } },
+
 { "crset",   XL(19,289), XL_MASK,      PPCCOM,         { BT, BAT, BBA } },
 { "creqv",   XL(19,289), XL_MASK,      COM,            { BT, BA, BB } },
 
@@ -3320,7 +3328,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "ldx",     X(31,21), X_MASK,         PPC64,          { RT, RA0, RB } },
 
-{ "icbt",    X(31,22), X_MASK,         BOOKE,          { CT, RA, RB } },
+{ "icbt",    X(31,22), X_MASK,         BOOKE|PPCE300,  { CT, RA, RB } },
 { "icbt",    X(31,262),        XRT_MASK,       PPC403,         { RA, RB } },
 
 { "lwzx",    X(31,23), X_MASK,         PPCCOM,         { RT, RA0, RB } },
@@ -3435,6 +3443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lbzux",   X(31,119),        X_MASK,         COM,            { RT, RAL, RB } },
 
+{ "popcntb", X(31,122), XRB_MASK,      POWER5,         { RA, RS } },
+
 { "not",     XRC(31,124,0), X_MASK,    COM,            { RA, RS, RBS } },
 { "nor",     XRC(31,124,0), X_MASK,    COM,            { RA, RS, RB } },
 { "not.",    XRC(31,124,1), X_MASK,    COM,            { RA, RS, RBS } },
@@ -4512,6 +4522,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "fmuls",   A(59,25,0), AFRB_MASK,    PPC,            { FRT, FRA, FRC } },
 { "fmuls.",  A(59,25,1), AFRB_MASK,    PPC,            { FRT, FRA, FRC } },
 
+{ "fsqrtes",  A(59,26,0), AFRAFRC_MASK,        POWER5,         { FRT, FRB } },
+{ "fsqrtes.", A(59,26,1), AFRAFRC_MASK,        POWER5,         { FRT, FRB } },
+
 { "fmsubs",  A(59,28,0), A_MASK,       PPC,            { FRT,FRA,FRC,FRB } },
 { "fmsubs.", A(59,28,1), A_MASK,       PPC,            { FRT,FRA,FRC,FRB } },
 
@@ -4583,6 +4596,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "fsel",    A(63,23,0), A_MASK,       PPC,            { FRT,FRA,FRC,FRB } },
 { "fsel.",   A(63,23,1), A_MASK,       PPC,            { FRT,FRA,FRC,FRB } },
 
+{ "fre",     A(63,24,0), AFRAFRC_MASK, POWER5,         { FRT, FRB } },
+{ "fre.",    A(63,24,1), AFRAFRC_MASK, POWER5,         { FRT, FRB } },
+
 { "fmul",    A(63,25,0), AFRB_MASK,    PPCCOM,         { FRT, FRA, FRC } },
 { "fm",      A(63,25,0), AFRB_MASK,    PWRCOM,         { FRT, FRA, FRC } },
 { "fmul.",   A(63,25,1), AFRB_MASK,    PPCCOM,         { FRT, FRA, FRC } },