/* ppc-opc.c -- PowerPC opcode list
- Copyright (c) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
+ Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
#define DS D + 1
- { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ { 16, 0, insert_ds, extract_ds,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The E field in a wrteei instruction. */
#define E DS + 1
#define LIA LI + 1
{ 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+ /* The LS field in an X (sync) form instruction. */
+#define LS LIA + 1
+ { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+
/* The MB field in an M form instruction. */
-#define MB LIA + 1
+#define MB LS + 1
#define MB_MASK (0x1f << 6)
{ 5, 6, 0, 0, 0 },
/* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1
#define VA_MASK (0x1f << 16)
- {5, 16, 0, 0, PPC_OPERAND_VR},
+ { 5, 16, 0, 0, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1
#define VB_MASK (0x1f << 11)
- {5, 11, 0, 0, PPC_OPERAND_VR},
+ { 5, 11, 0, 0, PPC_OPERAND_VR },
/* The VC field in a VA form instruction. */
#define VC VB + 1
#define VC_MASK (0x1f << 6)
- {5, 6, 0, 0, PPC_OPERAND_VR},
+ { 5, 6, 0, 0, PPC_OPERAND_VR },
/* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1
#define VS VD
#define VD_MASK (0x1f << 21)
- {5, 21, 0, 0, PPC_OPERAND_VR},
+ { 5, 21, 0, 0, PPC_OPERAND_VR },
/* The SIMM field in a VX form instruction. */
#define SIMM VD + 1
long value;
const char **errmsg ATTRIBUTE_UNUSED;
{
+ if ((value & 3) != 0 && errmsg != NULL)
+ *errmsg = _("offset not a multiple of 4");
return insn | (value & 0xfffc);
}
/* me: location of last 1->0 transition */
/* count: # transitions */
- for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
+ for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
{
if ((uval & mask) && !last)
{
#define VX_MASK VX(0x3f, 0x7ff)
/* An VA form instruction. */
-#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
+#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
/* The mask for an VA form instruction. */
-#define VXA_MASK VXA(0x3f, 0x7f)
+#define VXA_MASK VXA(0x3f, 0x3f)
/* An VXR form instruction. */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
#define XTO_MASK (X_MASK | TO_MASK)
+/* An X form tlb instruction with the SH field specified. */
+#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
+#define XTLB_MASK (X_MASK | SH_MASK)
+
+/* An X form sync instruction. */
+#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
+
+/* An X form sync instruction with everything filled in except the LS field. */
+#define XSYNC_MASK (0xff9fffff)
+
/* An XFL form instruction. */
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
#define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
#define PPCONLY PPC_OPCODE_PPC
#define PPC403 PPC
+#define PPC405 PPC403
#define PPC750 PPC
#define PPC860 PPC
#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
-
+
+{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
+{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
+{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
+{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
+{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
+{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
+{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslw", VX(4, 338), VX_MASK, PPCVEC, { VD, VA, VB } },
+{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
+{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
+
{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
-{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
+{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
+{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
+
{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
-{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
+{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
+
+{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
+{ "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } },
+
{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
+{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
+
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
-{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
-
{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
-{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
+{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
+{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
+{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
+{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
+{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
-{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
-{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
-{ "mficdbdr",XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
+{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
+{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
+{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
+{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
+{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
+{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
+{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
+{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
+{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
+{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
+{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
+{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
+{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
+{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
-{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
+{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
+{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
+{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
+
{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
-{ "mtummcr0", XSPR(31,451,936), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc1", XSPR(31,451,937), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc2", XSPR(31,451,938), XSPR_MASK, PPC750, { RT } },
-{ "mtusia", XSPR(31,451,939), XSPR_MASK, PPC750, { RT } },
-{ "mtummcr1", XSPR(31,451,940), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc3", XSPR(31,451,941), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc4", XSPR(31,451,942), XSPR_MASK, PPC750, { RT } },
-{ "mtmmcr0", XSPR(31,451,952), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc1", XSPR(31,451,953), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc2", XSPR(31,451,954), XSPR_MASK, PPC750, { RT } },
-{ "mtsia", XSPR(31,451,955), XSPR_MASK, PPC750, { RT } },
-{ "mtmmcr1", XSPR(31,451,956), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc3", XSPR(31,451,957), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc4", XSPR(31,451,958), XSPR_MASK, PPC750, { RT } },
-{ "mtl2cr", XSPR(31,451,1017), XSPR_MASK, PPC750, { RT } },
-{ "mtictc", XSPR(31,451,1019), XSPR_MASK, PPC750, { RT } },
-{ "mtthrm1", XSPR(31,451,1020), XSPR_MASK, PPC750, { RT } },
-{ "mtthrm2", XSPR(31,451,1021), XSPR_MASK, PPC750, { RT } },
-{ "mtthrm3", XSPR(31,451,1022), XSPR_MASK, PPC750, { RT } },
-{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
+{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
+{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
+{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
+{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
+{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
+{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
+{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
+{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
+{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
+{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
+{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
+{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
+{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
+{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
+{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
+{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
+{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
+{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
+{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
+{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
+{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
+{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
+{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
+{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
+{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
+{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
+{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
+{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
-{ "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } },
+{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
+{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
+{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
+{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
+
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
+{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
+
{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
+{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
+
{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
+{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
+{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } },
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
-{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
+{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
+
+{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
+{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
projects / deliverable / binutils-gdb.git / blobdiff