/* ppc-opc.c -- PowerPC opcode list
- Copyright 1994, 1995, 1996, 1997, 1998, 2000
+ Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
#define DS D + 1
- { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ { 16, 0, insert_ds, extract_ds,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The E field in a wrteei instruction. */
#define E DS + 1
#define LIA LI + 1
{ 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+ /* The LS field in an X (sync) form instruction. */
+#define LS LIA + 1
+ { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+
/* The MB field in an M form instruction. */
-#define MB LIA + 1
+#define MB LS + 1
#define MB_MASK (0x1f << 6)
{ 5, 6, 0, 0, 0 },
/* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1
#define VA_MASK (0x1f << 16)
- {5, 16, 0, 0, PPC_OPERAND_VR},
+ { 5, 16, 0, 0, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1
#define VB_MASK (0x1f << 11)
- {5, 11, 0, 0, PPC_OPERAND_VR},
+ { 5, 11, 0, 0, PPC_OPERAND_VR },
/* The VC field in a VA form instruction. */
#define VC VB + 1
#define VC_MASK (0x1f << 6)
- {5, 6, 0, 0, PPC_OPERAND_VR},
+ { 5, 6, 0, 0, PPC_OPERAND_VR },
/* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1
#define VS VD
#define VD_MASK (0x1f << 21)
- {5, 21, 0, 0, PPC_OPERAND_VR},
+ { 5, 21, 0, 0, PPC_OPERAND_VR },
/* The SIMM field in a VX form instruction. */
#define SIMM VD + 1
long value;
const char **errmsg ATTRIBUTE_UNUSED;
{
+ if ((value & 3) != 0 && errmsg != NULL)
+ *errmsg = _("offset not a multiple of 4");
return insn | (value & 0xfffc);
}
/* me: location of last 1->0 transition */
/* count: # transitions */
- for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
+ for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
{
if ((uval & mask) && !last)
{
#define VX_MASK VX(0x3f, 0x7ff)
/* An VA form instruction. */
-#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
+#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
/* The mask for an VA form instruction. */
-#define VXA_MASK VXA(0x3f, 0x7f)
+#define VXA_MASK VXA(0x3f, 0x3f)
/* An VXR form instruction. */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
#define XTLB_MASK (X_MASK | SH_MASK)
+/* An X form sync instruction. */
+#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
+
+/* An X form sync instruction with everything filled in except the LS field. */
+#define XSYNC_MASK (0xff9fffff)
+
/* An XFL form instruction. */
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
-{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
+{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
+{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
+
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
-{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
-
{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
+{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
+
{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
-{ "mtummcr0", XSPR(31,451,936), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc1", XSPR(31,451,937), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc2", XSPR(31,451,938), XSPR_MASK, PPC750, { RT } },
-{ "mtusia", XSPR(31,451,939), XSPR_MASK, PPC750, { RT } },
-{ "mtummcr1", XSPR(31,451,940), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc3", XSPR(31,451,941), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc4", XSPR(31,451,942), XSPR_MASK, PPC750, { RT } },
-{ "mtmmcr0", XSPR(31,451,952), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc1", XSPR(31,451,953), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc2", XSPR(31,451,954), XSPR_MASK, PPC750, { RT } },
-{ "mtsia", XSPR(31,451,955), XSPR_MASK, PPC750, { RT } },
-{ "mtmmcr1", XSPR(31,451,956), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc3", XSPR(31,451,957), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc4", XSPR(31,451,958), XSPR_MASK, PPC750, { RT } },
-{ "mtl2cr", XSPR(31,451,1017), XSPR_MASK, PPC750, { RT } },
-{ "mtictc", XSPR(31,451,1019), XSPR_MASK, PPC750, { RT } },
-{ "mtthrm1", XSPR(31,451,1020), XSPR_MASK, PPC750, { RT } },
-{ "mtthrm2", XSPR(31,451,1021), XSPR_MASK, PPC750, { RT } },
-{ "mtthrm3", XSPR(31,451,1022), XSPR_MASK, PPC750, { RT } },
{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
+{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
+{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
+{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
+{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
+{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
+{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
+{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
+{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
+{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
+{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
+{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
+{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
+{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
-{ "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } },
+{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
+{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
+{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
+{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
+
{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
+{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
+
{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },