2005, 2006, 2007 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
- This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of the GNU opcodes library.
- GDB, GAS, and the GNU binutils are free software; you can redistribute
- them and/or modify them under the terms of the GNU General Public
- License as published by the Free Software Foundation; either version
- 2, or (at your option) any later version.
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
- GDB, GAS, and the GNU binutils are distributed in the hope that they
- will be useful, but WITHOUT ANY WARRANTY; without even the implied
- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
- the GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
- along with this file; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
\f
/* The operands table.
- The fields are bits, shift, insert, extract, flags.
+ The fields are bitm, shift, insert, extract, flags.
We used to put parens around the various additions, like the one
for BA just below. However, that caused trouble with feeble
/* The BA field in an XL form instruction. */
#define BA UNUSED + 1
-#define BA_MASK (0x1f << 16)
+ /* The BI field in a B form or XL form instruction. */
+#define BI BA
+#define BI_MASK (0x1f << 16)
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same
/* The BF field in an X or XL form instruction. */
#define BF BDPA + 1
+ /* The CRFD field in an X form instruction. */
+#define CRFD BF
{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
+ /* The BF field in an X or XL form instruction. */
+#define BFF BF + 1
+ { 0x7, 23, NULL, NULL, 0 },
+
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
-#define OBF BF + 1
+#define OBF BFF + 1
{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
#define BFA OBF + 1
{ 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
- /* The BI field in a B form or XL form instruction. */
-#define BI BFA + 1
-#define BI_MASK (0x1f << 16)
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
-
/* The BO field in a B form instruction. Certain values are
illegal. */
-#define BO BI + 1
+#define BO BFA + 1
#define BO_MASK (0x1f << 21)
{ 0x1f, 21, insert_bo, extract_bo, 0 },
/* The CRB field in an X form instruction. */
#define CRB CR + 1
+ /* The MB field in an M form instruction. */
+#define MB CRB
+#define MB_MASK (0x1f << 6)
{ 0x1f, 6, NULL, NULL, 0 },
- /* The CRFD field in an X form instruction. */
-#define CRFD CRB + 1
- { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
-
/* The CRFS field in an X form instruction. */
-#define CRFS CRFD + 1
+#define CRFS CRB + 1
{ 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
/* The CT field in an X form instruction. */
#define CT CRFS + 1
+ /* The MO field in an mbar instruction. */
+#define MO CT
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The E field in a wrteei instruction. */
+ /* And the W bit in the pair singles instructions. */
#define E DS + 1
+#define PSW E
{ 0x1, 15, NULL, NULL, 0 },
/* The FL1 field in a POWER SC form instruction. */
#define FL1 E + 1
+ /* The U field in an X form instruction. */
+#define U FL1
{ 0xf, 12, NULL, NULL, 0 },
/* The FL2 field in a POWER SC form instruction. */
/* The FXM field in an XFX instruction. */
#define FXM FRS + 1
-#define FXM_MASK (0xff << 12)
{ 0xff, 12, insert_fxm, extract_fxm, 0 },
/* Power4 version for mfcr. */
#define LS LIA + 1
{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
- /* The MB field in an M form instruction. */
-#define MB LS + 1
-#define MB_MASK (0x1f << 6)
- { 0x1f, 6, NULL, NULL, 0 },
-
/* The ME field in an M form instruction. */
-#define ME MB + 1
+#define ME LS + 1
#define ME_MASK (0x1f << 1)
{ 0x1f, 1, NULL, NULL, 0 },
description in opcode/ppc.h for what this means. */
#define MBE ME + 1
{ 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
- { 0xff, 0, insert_mbe, extract_mbe, 0 },
+ { -1, 0, insert_mbe, extract_mbe, 0 },
/* The MB or ME field in an MD or MDS form instruction. The high
bit is wrapped to the low end. */
#define MB6_MASK (0x3f << 5)
{ 0x3f, 5, insert_mb6, extract_mb6, 0 },
- /* The MO field in an mbar instruction. */
-#define MO MB6 + 1
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
/* The NB field in an X form instruction. The value 32 is stored as
0. */
-#define NB MO + 1
+#define NB MB6 + 1
{ 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
/* The NSI field in a D form instruction. This is the same as the
#define RT_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
- /* The RS field of the DS form stq instruction, which has special
- value restrictions. */
+ /* The RS and RT fields of the DS form stq instruction, which have
+ special value restrictions. */
#define RSQ RS + 1
- { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RT field of the DQ form lq instruction, which has special
- value restrictions. */
-#define RTQ RSQ + 1
+#define RTQ RSQ
{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
/* The RS field of the tlbwe instruction, which is optional. */
-#define RSO RTQ + 1
+#define RSO RSQ + 1
#define RTO RSO
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
/* The SH field in an X or M form instruction. */
#define SH RSO + 1
#define SH_MASK (0x1f << 11)
+ /* The other UIMM field in a EVX form instruction. */
+#define EVUIMM SH
{ 0x1f, 11, NULL, NULL, 0 },
/* The SH field in an MD form instruction. This is split. */
/* The STRM field in an X AltiVec form instruction. */
#define STRM SR + 1
-#define STRM_MASK (0x3 << 21)
{ 0x3, 21, NULL, NULL, 0 },
/* The SV field in a POWER SC form instruction. */
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
- /* The U field in an X form instruction. */
-#define U TO + 1
- { 0xf, 12, NULL, NULL, 0 },
-
/* The UI field in a D form instruction. */
-#define UI U + 1
+#define UI TO + 1
{ 0xffff, 0, NULL, NULL, 0 },
/* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1
-#define VA_MASK (0x1f << 16)
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1
-#define VB_MASK (0x1f << 11)
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
/* The VC field in a VA form instruction. */
#define VC VB + 1
-#define VC_MASK (0x1f << 6)
{ 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
/* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1
#define VS VD
-#define VD_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
- /* The SIMM field in a VX form instruction. */
+ /* The SIMM field in a VX form instruction, and TE in Z form. */
#define SIMM VD + 1
+#define TE SIMM
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
- /* The UIMM field in a VX form instruction, and TE in Z form. */
+ /* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
-#define TE UIMM
{ 0x1f, 16, NULL, NULL, 0 },
/* The SHB field in a VA form instruction. */
#define SHB UIMM + 1
{ 0xf, 6, NULL, NULL, 0 },
- /* The other UIMM field in a EVX form instruction. */
-#define EVUIMM SHB + 1
- { 0x1f, 11, NULL, NULL, 0 },
-
/* The other UIMM field in a half word EVX form instruction. */
-#define EVUIMM_2 EVUIMM + 1
+#define EVUIMM_2 SHB + 1
{ 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
/* The other UIMM field in a word EVX form instruction. */
/* The WS field. */
#define WS EVUIMM_8 + 1
-#define WS_MASK (0x7 << 11)
{ 0x7, 11, NULL, NULL, 0 },
- /* The L field in an mtmsrd or A form instruction. */
-#define MTMSRD_L WS + 1
-#define A_L MTMSRD_L
+ /* PowerPC paired singles extensions. */
+ /* W bit in the pair singles instructions for x type instructions. */
+#define PSWM WS + 1
+ { 0x1, 10, 0, 0, 0 },
+
+ /* IDX bits for quantization in the pair singles instructions. */
+#define PSQ PSWM + 1
+ { 0x7, 12, 0, 0, 0 },
+
+ /* IDX bits for quantization in the pair singles x-type instructions. */
+#define PSQM PSQ + 1
+ { 0x7, 7, 0, 0, 0 },
+
+ /* Smaller D field for quantization in the pair singles instructions. */
+#define PSD PSQM + 1
+ { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
+#define A_L PSD + 1
+#define W A_L
+#define MTMSRD_L W
{ 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
-#define RMC A_L + 1
+#define RMC MTMSRD_L + 1
{ 0x3, 9, NULL, NULL, 0 },
#define R RMC + 1
#define DGM DCM
{ 0x3f, 10, NULL, NULL, 0 },
- /* The L field in an X form with the RT field fixed instruction. */
-#define XRT_L SH16 + 1
- { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
/* The EH field in larx instruction. */
-#define EH XRT_L + 1
+#define EH SH16 + 1
{ 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+ /* The L field in an mtfsf or XFL form instruction. */
+#define XFL_L EH + 1
+ { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
/* An X_MASK with the RA field fixed. */
#define XRA_MASK (X_MASK | RA_MASK)
+/* An XRA_MASK with the W field clear. */
+#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
+
/* An X_MASK with the RB field fixed. */
#define XRB_MASK (X_MASK | RB_MASK)
/* An XFL form instruction. */
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
-#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
+#define XFL_MASK XFL (0x3f, 0x3ff, 1)
/* An X form isel instruction. */
#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
/* An XO_MASK with the RB field fixed. */
#define XORB_MASK (XO_MASK | RB_MASK)
+/* An XOPS form instruction for paired singles. */
+#define XOPS(op, xop, rc) \
+ (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
+#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
+
+
/* An XS form instruction. */
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
#define XS_MASK XS (0x3f, 0x1ff, 1)
#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define XUC_MASK XUC(0x3f, 0x1f)
+/* An XW form instruction. */
+#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
+/* The mask for a G form instruction. rc not supported at present. */
+#define XW_MASK XW (0x3f, 0x3f, 0)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
#define PPC405 PPC403
#define PPC440 PPC_OPCODE_440
#define PPC750 PPC
+#define PPC7450 PPC
#define PPC860 PPC
+#define PPCPS PPC_OPCODE_PPCPS
#define PPCVEC PPC_OPCODE_ALTIVEC
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
+{ "dcbz_l", X(4,1014), XRT_MASK, PPCPS, { RA, RB } },
+{ "ps_cmpu0", X(4 ,0), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
+{ "psq_lx", XW(4,6,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{ "psq_stx", XW(4,7,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{ "ps_sum0", A(4 ,10,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sum0.", A(4 ,10,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sum1", A(4 ,11,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sum1.", A(4 ,11,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_muls0", A(4 ,12,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_muls0.", A(4 ,12,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_muls1", A(4 ,13,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_muls1.", A(4 ,13,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_madds0", A(4 ,14,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madds0.", A(4 ,14,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madds1", A(4 ,15,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madds1.", A(4 ,15,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_div", A(4,18,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_div.", A(4,18,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_sub", A(4,20,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_sub.", A(4,20,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_add", A(4,21,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_add.", A(4,21,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_sel", A(4,23,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sel.", A(4,23,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_res", A(4,24,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_res.", A(4,24,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_mul", A(4,25,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_mul.", A(4,25,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_rsqrte", A(4 ,26,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_rsqrte.", A(4 ,26,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_madd", A(4,29,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madd.", A(4,29,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_msub", A(4,28,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_msub.", A(4,28,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub", A(4,30,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub.", A(4,30,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd", A(4,31,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd.", A(4,31,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_cmpo0", X(4 ,32), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
+{ "psq_lux", XW(4,38,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{ "psq_stux", XW(4,39,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{ "ps_neg", XRC(4 ,40,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_neg.", XRC(4 ,40,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_cmpu1", X(4 ,64), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
+{ "ps_mr", XRC(4 ,72,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_mr.", XRC(4 ,72,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_cmpo1", X(4 ,96), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
+{ "ps_nabs", XRC(4 ,136,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_nabs.", XRC(4 ,136,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_abs", XRC(4,264,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_abs.", XRC(4,264,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge00.",XOPS(4,528,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge01.",XOPS(4,560,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge10.",XOPS(4,592,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge11.",XOPS(4,624,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
-{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
+{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
-{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
+{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
-{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
+{ "dcba", X(31,758), XRT_MASK, PPC405 | PPC7450 | BOOKE, { RA, RB } },
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
+{ "psq_l", OP(56), OP_MASK, PPCPS, { FRT, PSD, RA, PSW, PSQ } },
+
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
+{ "psq_lu", OP(57), OP_MASK, PPCPS, { FRT, PSD, RA, PSW, PSQ } },
+
{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
+{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
+{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
+
{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
-{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
+{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
-{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
-{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
+{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
+{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
-{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
-{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
+{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
+{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
projects / deliverable / binutils-gdb.git / blobdiff