/* ppc-opc.c -- PowerPC opcode list
- Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
+ Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
#include <stdio.h>
#include "sysdep.h"
\f
/* Local insertion and extraction functions. */
-static unsigned long insert_bat
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_bat
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bba
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_bba
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bd
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_bd
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bdm
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_bdm
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bdp
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_bdp
- PARAMS ((unsigned long, int, int *));
-static int valid_bo
- PARAMS ((long, int));
-static unsigned long insert_bo
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_bo
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_boe
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_boe
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ds
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_ds
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_de
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_de
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_des
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_des
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_li
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_li
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_mbe
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_mbe
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_mb6
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_mb6
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_nb
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_nb
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_nsi
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_nsi
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_pmrn
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_pmrn
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ral
- PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_ram
- PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_ras
- PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_rbs
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_rbs
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_sh6
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_sh6
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_spr
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_spr
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_tbr
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_tbr
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ev2
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_ev2
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ev4
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_ev4
- PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ev8
- PARAMS ((unsigned long, long, int, const char **));
-static long extract_ev8
- PARAMS ((unsigned long, int, int *));
+static unsigned long insert_bat (unsigned long, long, int, const char **);
+static long extract_bat (unsigned long, int, int *);
+static unsigned long insert_bba (unsigned long, long, int, const char **);
+static long extract_bba (unsigned long, int, int *);
+static unsigned long insert_bd (unsigned long, long, int, const char **);
+static long extract_bd (unsigned long, int, int *);
+static unsigned long insert_bdm (unsigned long, long, int, const char **);
+static long extract_bdm (unsigned long, int, int *);
+static unsigned long insert_bdp (unsigned long, long, int, const char **);
+static long extract_bdp (unsigned long, int, int *);
+static unsigned long insert_bo (unsigned long, long, int, const char **);
+static long extract_bo (unsigned long, int, int *);
+static unsigned long insert_boe (unsigned long, long, int, const char **);
+static long extract_boe (unsigned long, int, int *);
+static unsigned long insert_dq (unsigned long, long, int, const char **);
+static long extract_dq (unsigned long, int, int *);
+static unsigned long insert_ds (unsigned long, long, int, const char **);
+static long extract_ds (unsigned long, int, int *);
+static unsigned long insert_de (unsigned long, long, int, const char **);
+static long extract_de (unsigned long, int, int *);
+static unsigned long insert_des (unsigned long, long, int, const char **);
+static long extract_des (unsigned long, int, int *);
+static unsigned long insert_fxm (unsigned long, long, int, const char **);
+static long extract_fxm (unsigned long, int, int *);
+static unsigned long insert_li (unsigned long, long, int, const char **);
+static long extract_li (unsigned long, int, int *);
+static unsigned long insert_mbe (unsigned long, long, int, const char **);
+static long extract_mbe (unsigned long, int, int *);
+static unsigned long insert_mb6 (unsigned long, long, int, const char **);
+static long extract_mb6 (unsigned long, int, int *);
+static unsigned long insert_nb (unsigned long, long, int, const char **);
+static long extract_nb (unsigned long, int, int *);
+static unsigned long insert_nsi (unsigned long, long, int, const char **);
+static long extract_nsi (unsigned long, int, int *);
+static unsigned long insert_ral (unsigned long, long, int, const char **);
+static unsigned long insert_ram (unsigned long, long, int, const char **);
+static unsigned long insert_raq (unsigned long, long, int, const char **);
+static unsigned long insert_ras (unsigned long, long, int, const char **);
+static unsigned long insert_rbs (unsigned long, long, int, const char **);
+static long extract_rbs (unsigned long, int, int *);
+static unsigned long insert_rsq (unsigned long, long, int, const char **);
+static unsigned long insert_rtq (unsigned long, long, int, const char **);
+static unsigned long insert_sh6 (unsigned long, long, int, const char **);
+static long extract_sh6 (unsigned long, int, int *);
+static unsigned long insert_spr (unsigned long, long, int, const char **);
+static long extract_spr (unsigned long, int, int *);
+static unsigned long insert_tbr (unsigned long, long, int, const char **);
+static long extract_tbr (unsigned long, int, int *);
+static unsigned long insert_ev2 (unsigned long, long, int, const char **);
+static long extract_ev2 (unsigned long, int, int *);
+static unsigned long insert_ev4 (unsigned long, long, int, const char **);
+static long extract_ev4 (unsigned long, int, int *);
+static unsigned long insert_ev8 (unsigned long, long, int, const char **);
+static long extract_ev8 (unsigned long, int, int *);
\f
/* The operands table.
/* The CT field in an X form instruction. */
#define CT CRFS + 1
-#define RD CT
{ 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
#define DES DE + 1
{ 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ /* The DQ field in a DQ form instruction. This is like D, but the
+ lower four bits are forced to zero. */
+#define DQ DES + 1
+ { 16, 0, insert_dq, extract_dq,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
+
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
-#define DS DES + 1
+#define DS DQ + 1
{ 16, 0, insert_ds, extract_ds,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The FXM field in an XFX instruction. */
#define FXM FRS + 1
#define FXM_MASK (0xff << 12)
- { 8, 12, 0, 0, 0 },
+ { 8, 12, insert_fxm, extract_fxm, 0 },
+
+ /* Power4 version for mfcr. */
+#define FXM4 FXM + 1
+ { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
/* The L field in a D or X form instruction. */
-#define L FXM + 1
+#define L FXM4 + 1
{ 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SC form instruction. */
{ 16, 0, insert_nsi, extract_nsi,
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
- /* The PMRN field in an X form instruction. */
-#define PMRN NSI + 1
- { 16, 0, insert_pmrn, extract_pmrn, PPC_OPERAND_GPR },
-
- /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
-#define RA PMRN + 1
+ /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
+#define RA NSI + 1
#define RA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_GPR },
+ /* The RA field in the DQ form lq instruction, which has special
+ value restrictions. */
+#define RAQ RA + 1
+ { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
+
/* The RA field in a D or X form instruction which is an updating
load, which means that the RA field may not be zero and may not
equal the RT field. */
-#define RAL RA + 1
+#define RAL RAQ + 1
{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
/* The RA field in an lmw instruction, which has special value
#define RT_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_GPR },
+ /* The RS field of the DS form stq instruction, which has special
+ value restrictions. */
+#define RSQ RS + 1
+ { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
+
+ /* The RT field of the DQ form lq instruction, which has special
+ value restrictions. */
+#define RTQ RSQ + 1
+ { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+
/* The SH field in an X or M form instruction. */
-#define SH RS + 1
+#define SH RTQ + 1
#define SH_MASK (0x1f << 11)
{ 5, 11, 0, 0, 0 },
/* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */
#define SPR SISIGNOPT + 1
+#define PMR SPR
#define SPR_MASK (0x3ff << 11)
{ 10, 11, insert_spr, extract_spr, 0 },
#define UI U + 1
{ 16, 0, 0, 0, 0 },
- /* The VA field in a VA, VX or VXR form instruction. */
+ /* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1
#define VA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_VR },
- /* The VB field in a VA, VX or VXR form instruction. */
+ /* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1
#define VB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_VR },
- /* The VC field in a VA form instruction. */
+ /* The VC field in a VA form instruction. */
#define VC VB + 1
#define VC_MASK (0x1f << 6)
{ 5, 6, 0, 0, PPC_OPERAND_VR },
- /* The VD or VS field in a VA, VX, VXR or X form instruction. */
+ /* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1
#define VS VD
#define VD_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_VR },
- /* The SIMM field in a VX form instruction. */
+ /* The SIMM field in a VX form instruction. */
#define SIMM VD + 1
{ 5, 16, 0, 0, PPC_OPERAND_SIGNED},
- /* The UIMM field in a VX form instruction. */
+ /* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
{ 5, 16, 0, 0, 0 },
- /* The SHB field in a VA form instruction. */
+ /* The SHB field in a VA form instruction. */
#define SHB UIMM + 1
{ 4, 6, 0, 0, 0 },
- /* The other UIMM field in a EVX form instruction. */
+ /* The other UIMM field in a EVX form instruction. */
#define EVUIMM SHB + 1
{ 5, 11, 0, 0, 0 },
- /* The other UIMM field in a half word EVX form instruction. */
+ /* The other UIMM field in a half word EVX form instruction. */
#define EVUIMM_2 EVUIMM + 1
- { 5, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
+ { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
- /* The other UIMM field in a word EVX form instruction. */
+ /* The other UIMM field in a word EVX form instruction. */
#define EVUIMM_4 EVUIMM_2 + 1
- { 5, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
+ { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
- /* The other UIMM field in a double EVX form instruction. */
+ /* The other UIMM field in a double EVX form instruction. */
#define EVUIMM_8 EVUIMM_4 + 1
- { 8, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
+ { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
/* The WS field. */
#define WS EVUIMM_8 + 1
/*ARGSUSED*/
static unsigned long
-insert_bat (insn, value, dialect, errmsg)
- unsigned long insn;
- long value ATTRIBUTE_UNUSED;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_bat (unsigned long insn,
+ long value ATTRIBUTE_UNUSED,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (((insn >> 21) & 0x1f) << 16);
}
static long
-extract_bat (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid;
+extract_bat (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid)
{
- if (invalid != (int *) NULL
- && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
+ if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
*invalid = 1;
return 0;
}
/*ARGSUSED*/
static unsigned long
-insert_bba (insn, value, dialect, errmsg)
- unsigned long insn;
- long value ATTRIBUTE_UNUSED;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_bba (unsigned long insn,
+ long value ATTRIBUTE_UNUSED,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (((insn >> 16) & 0x1f) << 11);
}
static long
-extract_bba (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid;
+extract_bba (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid)
{
- if (invalid != (int *) NULL
- && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
+ if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
*invalid = 1;
return 0;
}
/*ARGSUSED*/
static unsigned long
-insert_bd (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_bd (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (value & 0xfffc);
}
/*ARGSUSED*/
static long
-extract_bd (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_bd (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}
/*ARGSUSED*/
static unsigned long
-insert_bdm (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_bdm (unsigned long insn,
+ long value,
+ int dialect,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
}
static long
-extract_bdm (insn, dialect, invalid)
- unsigned long insn;
- int dialect;
- int *invalid;
+extract_bdm (unsigned long insn,
+ int dialect,
+ int *invalid)
{
- if (invalid != (int *) NULL)
+ if ((dialect & PPC_OPCODE_POWER4) == 0)
{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
- *invalid = 1;
- }
- else
- {
- if ((insn & (0x17 << 21)) != (0x06 << 21)
- && (insn & (0x1d << 21)) != (0x18 << 21))
- *invalid = 1;
- }
+ if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
+ *invalid = 1;
+ }
+ else
+ {
+ if ((insn & (0x17 << 21)) != (0x06 << 21)
+ && (insn & (0x1d << 21)) != (0x18 << 21))
+ *invalid = 1;
}
+
return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}
/*ARGSUSED*/
static unsigned long
-insert_bdp (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_bdp (unsigned long insn,
+ long value,
+ int dialect,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
}
static long
-extract_bdp (insn, dialect, invalid)
- unsigned long insn;
- int dialect;
- int *invalid;
+extract_bdp (unsigned long insn,
+ int dialect,
+ int *invalid)
{
- if (invalid != (int *) NULL)
+ if ((dialect & PPC_OPCODE_POWER4) == 0)
{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
- *invalid = 1;
- }
- else
- {
- if ((insn & (0x17 << 21)) != (0x07 << 21)
- && (insn & (0x1d << 21)) != (0x19 << 21))
- *invalid = 1;
- }
+ if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
+ *invalid = 1;
}
+ else
+ {
+ if ((insn & (0x17 << 21)) != (0x07 << 21)
+ && (insn & (0x1d << 21)) != (0x19 << 21))
+ *invalid = 1;
+ }
+
return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}
/* Check for legal values of a BO field. */
static int
-valid_bo (value, dialect)
- long value;
- int dialect;
+valid_bo (long value, int dialect)
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
the field to an illegal value. */
static unsigned long
-insert_bo (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect;
- const char **errmsg;
+insert_bo (unsigned long insn,
+ long value,
+ int dialect,
+ const char **errmsg)
{
- if (errmsg != (const char **) NULL
- && ! valid_bo (value, dialect))
+ if (!valid_bo (value, dialect))
*errmsg = _("invalid conditional option");
return insn | ((value & 0x1f) << 21);
}
static long
-extract_bo (insn, dialect, invalid)
- unsigned long insn;
- int dialect;
- int *invalid;
+extract_bo (unsigned long insn,
+ int dialect,
+ int *invalid)
{
long value;
value = (insn >> 21) & 0x1f;
- if (invalid != (int *) NULL
- && ! valid_bo (value, dialect))
+ if (!valid_bo (value, dialect))
*invalid = 1;
return value;
}
extracting it, we force it to be even. */
static unsigned long
-insert_boe (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect;
- const char **errmsg;
+insert_boe (unsigned long insn,
+ long value,
+ int dialect,
+ const char **errmsg)
{
- if (errmsg != (const char **) NULL)
- {
- if (! valid_bo (value, dialect))
- *errmsg = _("invalid conditional option");
- else if ((value & 1) != 0)
- *errmsg = _("attempt to set y bit when using + or - modifier");
- }
+ if (!valid_bo (value, dialect))
+ *errmsg = _("invalid conditional option");
+ else if ((value & 1) != 0)
+ *errmsg = _("attempt to set y bit when using + or - modifier");
+
return insn | ((value & 0x1f) << 21);
}
static long
-extract_boe (insn, dialect, invalid)
- unsigned long insn;
- int dialect;
- int *invalid;
+extract_boe (unsigned long insn,
+ int dialect,
+ int *invalid)
{
long value;
value = (insn >> 21) & 0x1f;
- if (invalid != (int *) NULL
- && ! valid_bo (value, dialect))
+ if (!valid_bo (value, dialect))
*invalid = 1;
return value & 0x1e;
}
+/* The DQ field in a DQ form instruction. This is like D, but the
+ lower four bits are forced to zero. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_dq (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if ((value & 0xf) != 0)
+ *errmsg = _("offset not a multiple of 16");
+ return insn | (value & 0xfff0);
+}
+
+/*ARGSUSED*/
+static long
+extract_dq (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
+}
+
static unsigned long
-insert_ev2 (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char ** errmsg ATTRIBUTE_UNUSED;
+insert_ev2 (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value & 1) != 0 && errmsg != NULL)
+ if ((value & 1) != 0)
*errmsg = _("offset not a multiple of 2");
- if ((value > 62) != 0 && errmsg != NULL)
+ if ((value > 62) != 0)
*errmsg = _("offset greater than 62");
- return insn | ((value & 0xf8) << 8);
+ return insn | ((value & 0x3e) << 10);
}
static long
-extract_ev2 (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int * invalid ATTRIBUTE_UNUSED;
+extract_ev2 (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
- return (insn >> 8) & 0xf8;
+ return (insn >> 10) & 0x3e;
}
static unsigned long
-insert_ev4 (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char ** errmsg ATTRIBUTE_UNUSED;
+insert_ev4 (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value & 3) != 0 && errmsg != NULL)
+ if ((value & 3) != 0)
*errmsg = _("offset not a multiple of 4");
- if ((value > 124) != 0 && errmsg != NULL)
+ if ((value > 124) != 0)
*errmsg = _("offset greater than 124");
- return insn | ((value & 0xf8) << 8);
+ return insn | ((value & 0x7c) << 9);
}
static long
-extract_ev4 (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int * invalid ATTRIBUTE_UNUSED;
+extract_ev4 (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
- return (insn >> 8) & 0xf8;
+ return (insn >> 9) & 0x7c;
}
static unsigned long
-insert_ev8 (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char ** errmsg ATTRIBUTE_UNUSED;
+insert_ev8 (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value & 7) != 0 && errmsg != NULL)
+ if ((value & 7) != 0)
*errmsg = _("offset not a multiple of 8");
- if ((value > 248) != 0 && errmsg != NULL)
+ if ((value > 248) != 0)
*errmsg = _("offset greater than 248");
return insn | ((value & 0xf8) << 8);
}
static long
-extract_ev8 (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int * invalid ATTRIBUTE_UNUSED;
+extract_ev8 (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return (insn >> 8) & 0xf8;
}
/*ARGSUSED*/
static unsigned long
-insert_ds (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_ds (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value & 3) != 0 && errmsg != NULL)
+ if ((value & 3) != 0)
*errmsg = _("offset not a multiple of 4");
return insn | (value & 0xfffc);
}
/*ARGSUSED*/
static long
-extract_ds (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_ds (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}
/*ARGSUSED*/
static unsigned long
-insert_de (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_de (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value > 2047 || value < -2048) && errmsg != NULL)
+ if (value > 2047 || value < -2048)
*errmsg = _("offset not between -2048 and 2047");
return insn | ((value << 4) & 0xfff0);
}
/*ARGSUSED*/
static long
-extract_de (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_de (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return (insn & 0xfff0) >> 4;
}
/*ARGSUSED*/
static unsigned long
-insert_des (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_des (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value > 8191 || value < -8192) && errmsg != NULL)
+ if (value > 8191 || value < -8192)
*errmsg = _("offset not between -8192 and 8191");
- else if ((value & 3) != 0 && errmsg != NULL)
+ else if ((value & 3) != 0)
*errmsg = _("offset not a multiple of 4");
return insn | ((value << 2) & 0xfff0);
}
/*ARGSUSED*/
static long
-extract_des (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_des (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
}
+/* FXM mask in mfcr and mtcrf instructions. */
+
+static unsigned long
+insert_fxm (unsigned long insn,
+ long value,
+ int dialect,
+ const char **errmsg)
+{
+ /* If the optional field on mfcr is missing that means we want to use
+ the old form of the instruction that moves the whole cr. In that
+ case we'll have VALUE zero. There doesn't seem to be a way to
+ distinguish this from the case where someone writes mfcr %r3,0. */
+ if (value == 0)
+ ;
+
+ /* If only one bit of the FXM field is set, we can use the new form
+ of the instruction, which is faster. Unlike the Power4 branch hint
+ encoding, this is not backward compatible. */
+ else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
+ insn |= 1 << 20;
+
+ /* Any other value on mfcr is an error. */
+ else if ((insn & (0x3ff << 1)) == 19 << 1)
+ {
+ *errmsg = _("ignoring invalid mfcr mask");
+ value = 0;
+ }
+
+ return insn | ((value & 0xff) << 12);
+}
+
+static long
+extract_fxm (unsigned long insn,
+ int dialect,
+ int *invalid)
+{
+ long mask = (insn >> 12) & 0xff;
+
+ /* Is this a Power4 insn? */
+ if ((insn & (1 << 20)) != 0)
+ {
+ if ((dialect & PPC_OPCODE_POWER4) == 0)
+ *invalid = 1;
+ else
+ {
+ /* Exactly one bit of MASK should be set. */
+ if (mask == 0 || (mask & -mask) != mask)
+ *invalid = 1;
+ }
+ }
+
+ /* Check that non-power4 form of mfcr has a zero MASK. */
+ else if ((insn & (0x3ff << 1)) == 19 << 1)
+ {
+ if (mask != 0)
+ *invalid = 1;
+ }
+
+ return mask;
+}
+
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
/*ARGSUSED*/
static unsigned long
-insert_li (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_li (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
- if ((value & 3) != 0 && errmsg != (const char **) NULL)
+ if ((value & 3) != 0)
*errmsg = _("ignoring least significant bits in branch offset");
return insn | (value & 0x3fffffc);
}
/*ARGSUSED*/
static long
-extract_li (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_li (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
}
instruction which uses a field of this type. */
static unsigned long
-insert_mbe (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_mbe (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
unsigned long uval, mask;
int mb, me, mx, count, last;
if (uval == 0)
{
- if (errmsg != (const char **) NULL)
- *errmsg = _("illegal bitmask");
+ *errmsg = _("illegal bitmask");
return insn;
}
/* me: location of last 1->0 transition */
/* count: # transitions */
- for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
+ for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
{
if ((uval & mask) && !last)
{
me = 32;
if (count != 2 && (count != 0 || ! last))
- {
- if (errmsg != (const char **) NULL)
- *errmsg = _("illegal bitmask");
- }
+ *errmsg = _("illegal bitmask");
return insn | (mb << 6) | ((me - 1) << 1);
}
static long
-extract_mbe (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid;
+extract_mbe (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid)
{
long ret;
int mb, me;
int i;
- if (invalid != (int *) NULL)
- *invalid = 1;
+ *invalid = 1;
mb = (insn >> 6) & 0x1f;
me = (insn >> 1) & 0x1f;
{
ret = 0;
for (i = mb; i <= me; i++)
- ret |= (long) 1 << (31 - i);
+ ret |= 1L << (31 - i);
}
else if (mb == me + 1)
ret = ~0;
else /* (mb > me + 1) */
{
- ret = ~ (long) 0;
+ ret = ~0;
for (i = me + 1; i < mb; i++)
- ret &= ~ ((long) 1 << (31 - i));
+ ret &= ~(1L << (31 - i));
}
return ret;
}
/*ARGSUSED*/
static unsigned long
-insert_mb6 (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_mb6 (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | ((value & 0x1f) << 6) | (value & 0x20);
}
/*ARGSUSED*/
static long
-extract_mb6 (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_mb6 (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return ((insn >> 6) & 0x1f) | (insn & 0x20);
}
0. */
static unsigned long
-insert_nb (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_nb (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
if (value < 0 || value > 32)
*errmsg = _("value out of range");
/*ARGSUSED*/
static long
-extract_nb (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_nb (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
long ret;
/*ARGSUSED*/
static unsigned long
-insert_nsi (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
-{
- return insn | ((- value) & 0xffff);
-}
-
-static long
-extract_nsi (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid;
-{
- if (invalid != (int *) NULL)
- *invalid = 1;
- return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
-}
-
-/* The PMRN field in a X form instruction.
- This has 5+5 bits switched around. */
-
-static unsigned long
-insert_pmrn (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_nsi (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- return insn | ((value & 0x1f) << 16) | ((value & 0x3e) << 11);
+ return insn | (-value & 0xffff);
}
static long
-extract_pmrn (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_nsi (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid)
{
- return ((insn >> 16) & 0x1f) | ((insn >> 11) & 0x3e);
+ *invalid = 1;
+ return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
}
/* The RA field in a D or X form instruction which is an updating
equal the RT field. */
static unsigned long
-insert_ral (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_ral (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
if (value == 0
|| (unsigned long) value == ((insn >> 21) & 0x1f))
restrictions. */
static unsigned long
-insert_ram (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_ram (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
if ((unsigned long) value >= ((insn >> 21) & 0x1f))
*errmsg = _("index register in load range");
return insn | ((value & 0x1f) << 16);
}
+/* The RA field in the DQ form lq instruction, which has special
+ value restrictions. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_raq (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ long rtvalue = (insn & RT_MASK) >> 21;
+
+ if (value == rtvalue)
+ *errmsg = _("source and target register operands must be different");
+ return insn | ((value & 0x1f) << 16);
+}
+
/* The RA field in a D or X form instruction which is an updating
store or an updating floating point load, which means that the RA
field may not be zero. */
static unsigned long
-insert_ras (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg;
+insert_ras (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
{
if (value == 0)
*errmsg = _("invalid register operand when updating");
/*ARGSUSED*/
static unsigned long
-insert_rbs (insn, value, dialect, errmsg)
- unsigned long insn;
- long value ATTRIBUTE_UNUSED;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_rbs (unsigned long insn,
+ long value ATTRIBUTE_UNUSED,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (((insn >> 21) & 0x1f) << 11);
}
static long
-extract_rbs (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid;
+extract_rbs (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid)
{
- if (invalid != (int *) NULL
- && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
+ if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
*invalid = 1;
return 0;
}
+/* The RT field of the DQ form lq instruction, which has special
+ value restrictions. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rtq (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if ((value & 1) != 0)
+ *errmsg = _("target register operand must be even");
+ return insn | ((value & 0x1f) << 21);
+}
+
+/* The RS field of the DS form stq instruction, which has special
+ value restrictions. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rsq (unsigned long insn,
+ long value ATTRIBUTE_UNUSED,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if ((value & 1) != 0)
+ *errmsg = _("source register operand must be even");
+ return insn | ((value & 0x1f) << 21);
+}
+
/* The SH field in an MD form instruction. This is split. */
/*ARGSUSED*/
static unsigned long
-insert_sh6 (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_sh6 (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
}
/*ARGSUSED*/
static long
-extract_sh6 (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_sh6 (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
}
lower 5 bits are stored in the upper 5 and vice- versa. */
static unsigned long
-insert_spr (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_spr (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
}
static long
-extract_spr (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_spr (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
}
#define TB (268)
static unsigned long
-insert_tbr (insn, value, dialect, errmsg)
- unsigned long insn;
- long value;
- int dialect ATTRIBUTE_UNUSED;
- const char **errmsg ATTRIBUTE_UNUSED;
+insert_tbr (unsigned long insn,
+ long value,
+ int dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
if (value == 0)
value = TB;
}
static long
-extract_tbr (insn, dialect, invalid)
- unsigned long insn;
- int dialect ATTRIBUTE_UNUSED;
- int *invalid ATTRIBUTE_UNUSED;
+extract_tbr (unsigned long insn,
+ int dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
{
long ret;
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
-/* An VX form instruction. */
+/* An VX form instruction. */
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
-/* The mask for an VX form instruction. */
+/* The mask for an VX form instruction. */
#define VX_MASK VX(0x3f, 0x7ff)
-/* An VA form instruction. */
+/* An VA form instruction. */
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
-/* The mask for an VA form instruction. */
+/* The mask for an VA form instruction. */
#define VXA_MASK VXA(0x3f, 0x3f)
-/* An VXR form instruction. */
+/* An VXR form instruction. */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
-/* The mask for a VXR form instruction. */
+/* The mask for a VXR form instruction. */
#define VXR_MASK VXR(0x3f, 0x3ff, 1)
/* An X form instruction. */
/* An X_MASK with the RA and RB fields fixed. */
#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
-/* An XRARB_MASK, but with the L bit clear. */
+/* An XRARB_MASK, but with the L bit clear. */
#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
/* An X_MASK with the RT and RA fields fixed. */
#define XS_MASK XS (0x3f, 0x1ff, 1)
/* A mask for the FXM version of an XFX form instruction. */
-#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
+#define XFXFXM_MASK (X_MASK | (1 << 11))
/* An XFX form instruction with the FXM field filled in. */
#define XFXM(op, xop, fxm) \
/* Smaller names for the flags so each entry in the opcodes table will
fit on a single line. */
#undef PPC
-#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
-#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
+#define PPC PPC_OPCODE_PPC
+#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
-#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
-#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
-#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
-#define PPCONLY PPC_OPCODE_PPC
+#define POWER4 PPC_OPCODE_POWER4
+#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
+#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
#define PPC403 PPC_OPCODE_403
#define PPC405 PPC403
+#define PPC440 PPC_OPCODE_440
#define PPC750 PPC
#define PPC860 PPC
-#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
-#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
-#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
-#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
-#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
-#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
-#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
-#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
-#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
+#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
+#define POWER PPC_OPCODE_POWER
+#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
+#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
+#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
+#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
+#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
#define MFDEC1 PPC_OPCODE_POWER
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
#define BOOKE PPC_OPCODE_BOOKE
sorted by major opcode. */
const struct powerpc_opcode powerpc_opcodes[] = {
+{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
-{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
-{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
-{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
-{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
-{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
-{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
-{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
+{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RD, RB, UIMM } },
-{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RD, RB, RA } },
-{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RD, UIMM, RB } },
-{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RD, RB, UIMM } },
-{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RD, RA } },
-{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RD, RA } },
-{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RD, RA } },
-{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RD, RA } },
-{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RD, RA } },
-{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RD, RA } },
-{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RD, RA } },
-
-{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RD, RA, RB } },
+{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
+{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
+{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
+{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
+{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
+{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
+{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
+{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
+{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
+{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
+{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
+
+{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
-{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RD, RA, RB } },
+{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
-{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
-{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
-{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
-{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
-{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RD, SIMM } },
-{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RD, SIMM } },
+{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
+{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
+{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
+{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
+{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
+{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RD, RA, RB, CRFS } },
+{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } },
-{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } },
-{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RD, RA } },
-{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RD, RA, RB } },
+{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
+{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
+{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
+{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RD, RB } },
-{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RD, RB } },
-
-{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RD, RA } },
-{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RD, RA } },
-{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RD, RA } },
-{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RD, RA, RB } },
-{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RD, RA, RB } },
-{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RD, RA, RB } },
-{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RD, RA, RB } },
+{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
+{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
+
+{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
+{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
+{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
+{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RD, RB } },
-{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RD, RB } },
-{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RD, RB } },
-{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RD, RB } },
-{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RD, RB } },
-{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RD, RB } },
-{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RD, RB } },
-{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RD, RB } },
-{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RD, RB } },
-{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RD, RB } },
-
-{ "evsabs", VX(4, 708), VX_MASK, PPCSPE, { RD, RA } },
-{ "evsnabs", VX(4, 709), VX_MASK, PPCSPE, { RD, RA } },
-{ "evsneg", VX(4, 710), VX_MASK, PPCSPE, { RD, RA } },
-{ "evsadd", VX(4, 704), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evssub", VX(4, 705), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evsmul", VX(4, 712), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evsdiv", VX(4, 713), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evscmpgt", VX(4, 716), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evsgmplt", VX(4, 717), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evsgmpeq", VX(4, 718), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evststgt", VX(4, 732), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evststlt", VX(4, 733), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evststeq", VX(4, 734), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evscfui", VX(4, 720), VX_MASK, PPCSPE, { RD, RB } },
-{ "evscfsi", VX(4, 721), VX_MASK, PPCSPE, { RD, RB } },
-{ "evscfuf", VX(4, 722), VX_MASK, PPCSPE, { RD, RB } },
-{ "evscfsf", VX(4, 723), VX_MASK, PPCSPE, { RD, RB } },
-{ "evsctui", VX(4, 724), VX_MASK, PPCSPE, { RD, RB } },
-{ "evsctuiz", VX(4, 728), VX_MASK, PPCSPE, { RD, RB } },
-{ "evsctsi", VX(4, 725), VX_MASK, PPCSPE, { RD, RB } },
-{ "evsctsiz", VX(4, 730), VX_MASK, PPCSPE, { RD, RB } },
-{ "evsctuf", VX(4, 726), VX_MASK, PPCSPE, { RD, RB } },
-{ "evsctsf", VX(4, 727), VX_MASK, PPCSPE, { RD, RB } },
-
-{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwlssf", VX(4, 1091), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlssfa", VX(4, 1123), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlsmf", VX(4, 1099), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlsmfa", VX(4, 1131), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwhssfaa",VX(4, 1351), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhssmaa",VX(4, 1349), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmfaa",VX(4, 1359), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmiaa",VX(4, 1357), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhusiaa",VX(4, 1348), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhumiaa",VX(4, 1356), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwlssfaaw",VX(4, 1347), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlsmfaaw",VX(4, 1355), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwhssfan",VX(4, 1479), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhssian",VX(4, 1477), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmfan",VX(4, 1487), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhsmian",VX(4, 1485), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhusian",VX(4, 1476), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhumian",VX(4, 1484), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwlssfanw",VX(4, 1475), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlsmfanw",VX(4, 1483), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwhgssfaa",VX(4, 1383), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhgsmfaa",VX(4, 1391), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhgsmiaa",VX(4, 1381), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhgumiaa",VX(4, 1380), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwhgssfan",VX(4, 1511), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhgsmfan",VX(4, 1519), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhgsmian",VX(4, 1509), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwhgumian",VX(4, 1508), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RD, RA, RB } },
-
-{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RD, RA } },
-{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RD, RA } },
-{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RD, RA } },
-{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RD, RA } },
-
-{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RD, RA } },
-{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RD, RA } },
-{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RD, RA } },
-{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RD, RA } },
-
-{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RD, RA } },
-
-{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RD, RA, RB } },
-{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RD, RA, RB } },
+{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
+{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
+{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
+{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
+{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
+{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
+{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
+{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
+{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
+{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
+
+{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
+{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
+{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
+{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
+
+{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
+{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
+{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
+{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
+
+{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
+
+{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
+{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
-{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
+{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
-{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
+{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
-{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
-{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
-{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
-{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
-{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
-{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
-{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
-{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
-{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
-{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
-{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
-{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
+{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
+{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
+{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
+{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
+{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
+{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
+{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
+{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
+{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
+{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
+{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
+{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
+{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
+{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
+{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
+{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
+{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
+{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
+{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
+{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
+{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
+{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
+{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
+{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
+{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
+{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
+{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
+{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
-{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
+{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
+{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
+{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
+{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
+{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
+{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
+{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
+{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
+{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
-{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
-
+{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
-{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
-{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
+{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
+{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
+{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
-{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
+{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
-{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
+{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
+{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
+{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
-{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
+{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
+{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
+{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
+
{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
-{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
-{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
+{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
-{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
+{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
-{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
-{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
+{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
-{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
-
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
-{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
-{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
+{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
-{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMRN }},
+{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
+{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
-{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
+{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
+{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
+{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
+{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
+{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
+{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
+{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
+{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
+{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
+{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
+{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
+{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
+{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
+{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
+{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
+{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
+{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
+{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
+{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
+{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
+{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
-{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
-{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
-{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
-{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
-{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
-{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
-{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
-{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
-{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
-{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
-{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
-{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
-{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
-{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
-{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
-{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
+{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
-{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
-{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
-{ "mftb", X(31,371), X_MASK, BOOKE, { RT, TBR } },
-{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
-
{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
-{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
-{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
-{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
-{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
-{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
-{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
-{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
-{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
-{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
-{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
-{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
-{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
-{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
-{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
-{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
-{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
-{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
-{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
-{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
-{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
-{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
-{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
-{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
-{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
-{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
-{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
-{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
-{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
-{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
+{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
+{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
+{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
+{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
+{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
+{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
+{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
+{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
+{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
+{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
+{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
+{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
+{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
+{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
+{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
+{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
+{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
+{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
+{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
+{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
+{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
+{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
+{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
+{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
+{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
+{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
+{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
+{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
+{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
+{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
+{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
-{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
-{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
-{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
-{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
-{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
-{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
-{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
-{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
-{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
-{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
-{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
-{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
-{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
-{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
-{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
-{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
-{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
+{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
+{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
+{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
+{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
+{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
+{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
+{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
+{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
+{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
+{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
+{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
+{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
+{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
+{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
+{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
+{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
+{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
-{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
-{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
-{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
-{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
-{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
-{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
-{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
-{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
-{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
-{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
-{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
-{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
+{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
+{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
+{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
+{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
+{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
+{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
+{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
+{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
+{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
+{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
+{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
+{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
+{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
+{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
+{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
+{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
+{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
+{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
-{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RT } },
+{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
+{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
-{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
-{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
-{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
-{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
-{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
-{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
-{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
-{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
-{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
-{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
-{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
-{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
-{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
-{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
-{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
-{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
-{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
-{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
-{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
-{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
-{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
-{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
-{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
-{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
-{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
-{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
-{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
-{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
-{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
-{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
-{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
-{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
-{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
-{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
-{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
-{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
-{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
-{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
-{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
-{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
-{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
-{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
-{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
-{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
-{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
-{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
-{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
-{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
-{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
-{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
-{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
-{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
+{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
+{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
+{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
+{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
+{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
+{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
+{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
+{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
+{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
+{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
+{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
+{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
+{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
+{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
+{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
+{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
+{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
+{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
+{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
+{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
+{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
+{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
+{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
+{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
+{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
+{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
+{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
+{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
+{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
+{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
+{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
+{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
+{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
+{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
+{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
+{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
+{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
+{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
+{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
-{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
+{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
-{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMRN, RS }},
+{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
-{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
+{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
+{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
-{ "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } },
{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
-{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
-{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
+{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
+{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
-{ "mbar", X(31,854), 0xffffffff, BOOKE, { MO } },
-
-{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
-{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
+{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
+{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
-{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
-
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
+{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
+{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
-{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
-
-{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
-
-{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
+{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
+{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
+{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
-{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
+{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
+{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
+
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
+{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
+
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
-{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
-{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
+{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
+{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
projects / deliverable / binutils-gdb.git / blobdiff