/* The zero index is used to indicate the end of the list of
operands. */
#define UNUSED 0
- { 0, 0, 0, 0, 0 },
+ { 0, 0, NULL, NULL, 0 },
/* The BA field in an XL form instruction. */
#define BA UNUSED + 1
#define BA_MASK (0x1f << 16)
- { 5, 16, 0, 0, PPC_OPERAND_CR },
+ { 5, 16, NULL, NULL, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same
as the BT field in the same instruction. */
/* The BB field in an XL form instruction. */
#define BB BAT + 1
#define BB_MASK (0x1f << 11)
- { 5, 11, 0, 0, PPC_OPERAND_CR },
+ { 5, 11, NULL, NULL, PPC_OPERAND_CR },
/* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */
/* The BF field in an X or XL form instruction. */
#define BF BDPA + 1
- { 3, 23, 0, 0, PPC_OPERAND_CR },
+ { 3, 23, NULL, NULL, PPC_OPERAND_CR },
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
#define OBF BF + 1
- { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+ { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
#define BFA OBF + 1
- { 3, 18, 0, 0, PPC_OPERAND_CR },
+ { 3, 18, NULL, NULL, PPC_OPERAND_CR },
/* The BI field in a B form or XL form instruction. */
#define BI BFA + 1
#define BI_MASK (0x1f << 16)
- { 5, 16, 0, 0, PPC_OPERAND_CR },
+ { 5, 16, NULL, NULL, PPC_OPERAND_CR },
/* The BO field in a B form instruction. Certain values are
illegal. */
{ 5, 21, insert_boe, extract_boe, 0 },
#define BH BOE + 1
- { 2, 11, 0, 0, PPC_OPERAND_OPTIONAL },
+ { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The BT field in an X or XL form instruction. */
#define BT BH + 1
- { 5, 21, 0, 0, PPC_OPERAND_CR },
+ { 5, 21, NULL, NULL, PPC_OPERAND_CR },
/* The condition register number portion of the BI field in a B form
or XL form instruction. This is used for the extended
conditional branch mnemonics, which set the lower two bits of the
BI field. This field is optional. */
#define CR BT + 1
- { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+ { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The CRB field in an X form instruction. */
#define CRB CR + 1
- { 5, 6, 0, 0, 0 },
+ { 5, 6, NULL, NULL, 0 },
/* The CRFD field in an X form instruction. */
#define CRFD CRB + 1
- { 3, 23, 0, 0, PPC_OPERAND_CR },
+ { 3, 23, NULL, NULL, PPC_OPERAND_CR },
/* The CRFS field in an X form instruction. */
#define CRFS CRFD + 1
- { 3, 0, 0, 0, PPC_OPERAND_CR },
+ { 3, 0, NULL, NULL, PPC_OPERAND_CR },
/* The CT field in an X form instruction. */
#define CT CRFS + 1
- { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+ { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in
parentheses. */
#define D CT + 1
- { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The DE field in a DE form instruction. This is like D, but is 12
bits only. */
/* The E field in a wrteei instruction. */
#define E DS + 1
- { 1, 15, 0, 0, 0 },
+ { 1, 15, NULL, NULL, 0 },
/* The FL1 field in a POWER SC form instruction. */
#define FL1 E + 1
- { 4, 12, 0, 0, 0 },
+ { 4, 12, NULL, NULL, 0 },
/* The FL2 field in a POWER SC form instruction. */
#define FL2 FL1 + 1
- { 3, 2, 0, 0, 0 },
+ { 3, 2, NULL, NULL, 0 },
/* The FLM field in an XFL form instruction. */
#define FLM FL2 + 1
- { 8, 17, 0, 0, 0 },
+ { 8, 17, NULL, NULL, 0 },
/* The FRA field in an X or A form instruction. */
#define FRA FLM + 1
#define FRA_MASK (0x1f << 16)
- { 5, 16, 0, 0, PPC_OPERAND_FPR },
+ { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
/* The FRB field in an X or A form instruction. */
#define FRB FRA + 1
#define FRB_MASK (0x1f << 11)
- { 5, 11, 0, 0, PPC_OPERAND_FPR },
+ { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
/* The FRC field in an A form instruction. */
#define FRC FRB + 1
#define FRC_MASK (0x1f << 6)
- { 5, 6, 0, 0, PPC_OPERAND_FPR },
+ { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
/* The FRS field in an X form instruction or the FRT field in a D, X
or A form instruction. */
#define FRS FRC + 1
#define FRT FRS
- { 5, 21, 0, 0, PPC_OPERAND_FPR },
+ { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
/* The FXM field in an XFX instruction. */
#define FXM FRS + 1
/* The L field in a D or X form instruction. */
#define L FXM4 + 1
- { 1, 21, 0, 0, 0 },
+ { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SC form instruction. */
#define LEV L + 1
- { 7, 5, 0, 0, 0 },
+ { 7, 5, NULL, NULL, 0 },
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
/* The LS field in an X (sync) form instruction. */
#define LS LIA + 1
- { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+ { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The MB field in an M form instruction. */
#define MB LS + 1
#define MB_MASK (0x1f << 6)
- { 5, 6, 0, 0, 0 },
+ { 5, 6, NULL, NULL, 0 },
/* The ME field in an M form instruction. */
#define ME MB + 1
#define ME_MASK (0x1f << 1)
- { 5, 1, 0, 0, 0 },
+ { 5, 1, NULL, NULL, 0 },
/* The MB and ME fields in an M form instruction expressed a single
operand which is a bitmask indicating which bits to select. This
is a two operand form using PPC_OPERAND_NEXT. See the
description in opcode/ppc.h for what this means. */
#define MBE ME + 1
- { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
+ { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
{ 32, 0, insert_mbe, extract_mbe, 0 },
/* The MB or ME field in an MD or MDS form instruction. The high
/* The MO field in an mbar instruction. */
#define MO MB6 + 1
- { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+ { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The NB field in an X form instruction. The value 32 is stored as
0. */
/* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
#define RA NSI + 1
#define RA_MASK (0x1f << 16)
- { 5, 16, 0, 0, PPC_OPERAND_GPR },
+ { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
/* As above, but 0 in the RA field means zero, not r0. */
#define RA0 RA + 1
- { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
+ { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
/* The RA field in the DQ form lq instruction, which has special
value restrictions. */
#define RAQ RA0 + 1
- { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
+ { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
/* The RA field in a D or X form instruction which is an updating
load, which means that the RA field may not be zero and may not
equal the RT field. */
#define RAL RAQ + 1
- { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
+ { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
/* The RA field in an lmw instruction, which has special value
restrictions. */
#define RAM RAL + 1
- { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
+ { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
/* The RA field in a D or X form instruction which is an updating
store or an updating floating point load, which means that the RA
field may not be zero. */
#define RAS RAM + 1
- { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
+ { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
/* The RA field of the tlbwe instruction, which is optional. */
#define RAOPT RAS + 1
- { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
+ { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
/* The RB field in an X, XO, M, or MDS form instruction. */
#define RB RAOPT + 1
#define RB_MASK (0x1f << 11)
- { 5, 11, 0, 0, PPC_OPERAND_GPR },
+ { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
/* The RB field in an X form instruction when it must be the same as
the RS field in the instruction. This is used for extended
#define RS RBS + 1
#define RT RS
#define RT_MASK (0x1f << 21)
- { 5, 21, 0, 0, PPC_OPERAND_GPR },
+ { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
/* The RS field of the DS form stq instruction, which has special
value restrictions. */
#define RSQ RS + 1
- { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
+ { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
/* The RT field of the DQ form lq instruction, which has special
value restrictions. */
#define RTQ RSQ + 1
- { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
+ { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
/* The RS field of the tlbwe instruction, which is optional. */
#define RSO RTQ + 1
- { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
+ { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
/* The SH field in an X or M form instruction. */
#define SH RSO + 1
#define SH_MASK (0x1f << 11)
- { 5, 11, 0, 0, 0 },
+ { 5, 11, NULL, NULL, 0 },
/* The SH field in an MD form instruction. This is split. */
#define SH6 SH + 1
/* The SH field of the tlbwe instruction, which is optional. */
#define SHO SH6 + 1
- { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
+ { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The SI field in a D form instruction. */
#define SI SHO + 1
- { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
+ { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
/* The SI field in a D form instruction when we accept a wide range
of positive values. */
#define SISIGNOPT SI + 1
- { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+ { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
/* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */
/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
#define SPRBAT SPR + 1
#define SPRBAT_MASK (0x3 << 17)
- { 2, 17, 0, 0, 0 },
+ { 2, 17, NULL, NULL, 0 },
/* The SPRG register number in an XFX form m[ft]sprg instruction. */
#define SPRG SPRBAT + 1
#define SPRG_MASK (0x3 << 16)
- { 2, 16, 0, 0, 0 },
+ { 2, 16, NULL, NULL, 0 },
/* The SR field in an X form instruction. */
#define SR SPRG + 1
- { 4, 16, 0, 0, 0 },
+ { 4, 16, NULL, NULL, 0 },
/* The STRM field in an X AltiVec form instruction. */
#define STRM SR + 1
#define STRM_MASK (0x3 << 21)
- { 2, 21, 0, 0, 0 },
+ { 2, 21, NULL, NULL, 0 },
/* The SV field in a POWER SC form instruction. */
#define SV STRM + 1
- { 14, 2, 0, 0, 0 },
+ { 14, 2, NULL, NULL, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR
field, but it is optional. */
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define TO_MASK (0x1f << 21)
- { 5, 21, 0, 0, 0 },
+ { 5, 21, NULL, NULL, 0 },
/* The U field in an X form instruction. */
#define U TO + 1
- { 4, 12, 0, 0, 0 },
+ { 4, 12, NULL, NULL, 0 },
/* The UI field in a D form instruction. */
#define UI U + 1
- { 16, 0, 0, 0, 0 },
+ { 16, 0, NULL, NULL, 0 },
/* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1
#define VA_MASK (0x1f << 16)
- { 5, 16, 0, 0, PPC_OPERAND_VR },
+ { 5, 16, NULL, NULL, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1
#define VB_MASK (0x1f << 11)
- { 5, 11, 0, 0, PPC_OPERAND_VR },
+ { 5, 11, NULL, NULL, PPC_OPERAND_VR },
/* The VC field in a VA form instruction. */
#define VC VB + 1
#define VC_MASK (0x1f << 6)
- { 5, 6, 0, 0, PPC_OPERAND_VR },
+ { 5, 6, NULL, NULL, PPC_OPERAND_VR },
/* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1
#define VS VD
#define VD_MASK (0x1f << 21)
- { 5, 21, 0, 0, PPC_OPERAND_VR },
+ { 5, 21, NULL, NULL, PPC_OPERAND_VR },
/* The SIMM field in a VX form instruction. */
#define SIMM VD + 1
- { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
+ { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
/* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
- { 5, 16, 0, 0, 0 },
+ { 5, 16, NULL, NULL, 0 },
/* The SHB field in a VA form instruction. */
#define SHB UIMM + 1
- { 4, 6, 0, 0, 0 },
+ { 4, 6, NULL, NULL, 0 },
/* The other UIMM field in a EVX form instruction. */
#define EVUIMM SHB + 1
- { 5, 11, 0, 0, 0 },
+ { 5, 11, NULL, NULL, 0 },
/* The other UIMM field in a half word EVX form instruction. */
#define EVUIMM_2 EVUIMM + 1
/* The WS field. */
#define WS EVUIMM_8 + 1
#define WS_MASK (0x7 << 11)
- { 3, 11, 0, 0, 0 },
+ { 3, 11, NULL, NULL, 0 },
/* The L field in an mtmsrd instruction */
#define MTMSRD_L WS + 1
- { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
+ { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
};
{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
+
+ /* Double-precision opcodes. */
+ /* Some of these conflict with AltiVec, so move them before, since
+ PPCVEC includes the PPC_OPCODE_PPC set. */
+{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RA } },
+{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
+{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
+{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
+{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
+{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
+{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
+ /* End of double-precision opcodes. */
+
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
projects / deliverable / binutils-gdb.git / blobdiff