[gdb/testsuite] Fix gdb.fortran/nested-funcs-2.exp with gdbserver

[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 804d013e5b0ff53d2888f2f1ccb1f934d6f922ed..ed0a668ad64638cacf3d851ea7cb89209516c1ee 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2306,8 +2306,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define UIM3 IMM32 + 1
   { 0x7, 32, NULL, NULL, 0},
 
+  /* The UIM field in a vector eval prefix instruction.  */
+#define UIM8 UIM3 + 1
+  { 0xff, 32, NULL, NULL, 0},
+
   /* The IX field in xxsplti32dx.  */
-#define IX UIM3 + 1
+#define IX UIM8 + 1
   { 0x1, 17, NULL, NULL, 0 },
 
   /* The PMSK field in GER rank 8 prefix instructions.  */
@@ -3107,6 +3111,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 /* Mask for prefix vector permute insns.  */
 #define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
 #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
+#define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32))
 
 /* MMIRR:XX3-form 8-byte outer product instructions.  */
 #define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1)
@@ -4113,6 +4118,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vdivuq",     VX (4,  11),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"psq_lx",     XW (4,   6,0),  XW_MASK,     PPCPS,     0,              {FRT,RA,RB,PSWM,PSQM}},
 {"vmrghb",     VX (4,  12),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vstribl",    VXVA(4,13,0),   VXVA_MASK,   POWER10,   0,              {VD, VB}},
+{"vstribr",    VXVA(4,13,1),   VXVA_MASK,   POWER10,   0,              {VD, VB}},
+{"vstrihl",    VXVA(4,13,2),   VXVA_MASK,   POWER10,   0,              {VD, VB}},
+{"vstrihr",    VXVA(4,13,3),   VXVA_MASK,   POWER10,   0,              {VD, VB}},
 {"psq_stx",    XW (4,   7,0),  XW_MASK,     PPCPS,     0,              {FRS,RA,RB,PSWM,PSQM}},
 {"vpkuhum",    VX (4,  14),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vinsbvlx",   VX (4,  15),    VX_MASK,     POWER10,   0,              {VD, RA, VB}},
@@ -4288,6 +4297,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vexptefp",   VX (4, 394),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
 {"vdivsw",     VX (4, 395),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"vmrglw",     VX (4, 396),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vclrlb",     VX (4, 397),    VX_MASK,     POWER10,   0,              {VD, VA, RB}},
 {"vpkshss",    VX (4, 398),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vinswvrx",   VX (4, 399),    VX_MASK,     POWER10,   0,              {VD, RA, VB}},
 {"macchwsu",   XO (4, 204,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
@@ -4301,6 +4311,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmulld",     VX (4, 457),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"vlogefp",    VX (4, 458),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
 {"vdivsd",     VX (4, 459),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
+{"vclrrb",     VX (4, 461),    VX_MASK,     POWER10,   0,              {VD, VA, RB}},
 {"vpkswss",    VX (4, 462),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vinsd",      VX (4, 463),   VXUIMM4_MASK, POWER10,   0,              {VD, RB, UIMM4}},
 {"macchws",    XO (4, 236,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
@@ -4649,6 +4660,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhesmf",   VX (4,1035),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"evmhoumi",   VX (4,1036),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"vslo",       VX (4,1036),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vstribl.",   VXVA(4,1037,0), VXVA_MASK,   POWER10,   0,              {VD, VB}},
+{"vstribr.",   VXVA(4,1037,1), VXVA_MASK,   POWER10,   0,              {VD, VB}},
+{"vstrihl.",   VXVA(4,1037,2), VXVA_MASK,   POWER10,   0,              {VD, VB}},
+{"vstrihr.",   VXVA(4,1037,3), VXVA_MASK,   POWER10,   0,              {VD, VB}},
 {"evmhosmi",   VX (4,1037),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"evmhosmf",   VX (4,1039),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"machhwuo",   XO (4,  12,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
@@ -4738,6 +4753,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evaddsmiaaw",        VX (4,1225),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
 {"evsubfumiaaw",VX (4,1226),   VX_MASK,     PPCSPE,    0,              {RS, RA}},
 {"evsubfsmiaaw",VX (4,1227),   VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vgnb",       VX (4,1228),    VX_MASK,     POWER10,   0,              {RT, VB, UIMM3}},
 {"vpkudus",    VX (4,1230),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
 {"machhwso",   XO (4, 108,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"machhwso.",  XO (4, 108,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
@@ -4796,6 +4812,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlsmfaaw",        VX (4,1355),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
 {"evmwhumiaa", VX (4,1356),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
 {"vbpermq",    VX (4,1356),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcfuged",    VX (4,1357),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"evmwhsmiaa", VX (4,1357),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
 {"vpksdus",    VX (4,1358),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
 {"evmwhsmfaa", VX (4,1359),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
@@ -4834,6 +4851,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhesmianw",        VX (4,1417),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"evmhesmfanw",        VX (4,1419),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"evmhoumianw",        VX (4,1420),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vpextd",     VX (4,1421),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"evmhosmianw",        VX (4,1421),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"evmhosmfanw",        VX (4,1423),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
 {"macchwsuo",  XO (4, 204,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
@@ -4862,6 +4880,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlsmfanw",        VX (4,1483),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
 {"evmwhumian", VX (4,1484),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
 {"vbpermd",    VX (4,1484),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vpdepd",     VX (4,1485),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"evmwhsmian", VX (4,1485),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
 {"vpksdss",    VX (4,1486),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
 {"evmwhsmfan", VX (4,1487),    VX_MASK,     PPCSPE,    0,              {RD, RA, RB}},
@@ -4977,6 +4996,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vsubsws",    VX (4,1920),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vclzw",      VX (4,1922),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
 {"vpopcntw",   VX (4,1923),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vclzdm",     VX (4,1924),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"vcmpgtsw.",  VXR(4, 902,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi14fcm.",  APU(4, 963,0),  APU_MASK,    PPC440,    0,              {URT, URA, URB}},
 {"vcmpgtsq.",  VXR(4, 903,1),  VXR_MASK,    POWER10,   0,              {VD, VA, VB}},
@@ -4989,6 +5009,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"vclzd",      VX (4,1986),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
 {"vpopcntd",   VX (4,1987),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vctzdm",     VX (4,1988),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
 {"vcmpbfp.",   VXR(4, 966,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi15fcm.",  APU(4, 995,0),  APU_MASK,    PPC440,    0,              {URT, URA, URB}},
 {"vcmpgtsd.",  VXR(4, 967,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
@@ -6012,6 +6033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxsiwzx",    X(31,12),       XX1_MASK,    PPCVSX2,   0,              {XT6, RA0, RB}},
 
+{"lxvrbx",     X(31,13),       XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"isellt",     X(31,15),       X_MASK,      PPCISEL,   0,              {RT, RA0, RB}},
 
 {"tlbilxlpid", XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, 0,              {0}},
@@ -6066,6 +6089,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"lvehx",      X(31,39),       X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
 {"lhfcmx",     APU(31,39,0),   APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
+{"lxvrhx",     X(31,45),       XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"mviwsplt",   X(31,46),       X_MASK,      E6500,     0,              {VD, RA, RB}},
 
 {"iselgt",     X(31,47),       X_MASK,      PPCISEL,   0,              {RT, RA0, RB}},
@@ -6076,6 +6101,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxsiwax",    X(31,76),       XX1_MASK,    PPCVSX2,   0,              {XT6, RA0, RB}},
 
+{"lxvrwx",     X(31,77),       XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"iseleq",     X(31,79),       X_MASK,      PPCISEL,   0,              {RT, RA0, RB}},
 
 {"isel",       XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0,             {RT, RA0, RB, CRB}},
@@ -6102,6 +6129,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cntlzd",     XRC(31,58,0),   XRB_MASK,    PPC64,     0,              {RA, RS}},
 {"cntlzd.",    XRC(31,58,1),   XRB_MASK,    PPC64,     0,              {RA, RS}},
 
+{"cntlzdm",    X(31,59),       X_MASK,      POWER10,   0,              {RA, RS, RB}},
+
 {"andc",       XRC(31,60,0),   X_MASK,      COM,       0,              {RA, RS, RB}},
 {"andc.",      XRC(31,60,1),   X_MASK,      COM,       0,              {RA, RS, RB}},
 
@@ -6162,6 +6191,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mul",                XO(31,107,0,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
 {"mul.",       XO(31,107,0,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
+{"lxvrdx",     X(31,109),      XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"mvidsplt",   X(31,110),      X_MASK,      E6500,     0,              {VD, RA, RB}},
 
 {"mtsrdin",    X(31,114),      XRA_MASK,    PPC64,     0,              {RS, RB}},
@@ -6206,6 +6237,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stxsiwx",    X(31,140),      XX1_MASK,    PPCVSX2,   0,              {XS6, RA0, RB}},
 
+{"stxvrbx",    X(31,141),      XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"msgsndp",    XRTRA(31,142,0,0), XRTRA_MASK, POWER8,  0,              {RB}},
 {"dcbtstlse",  X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
 
@@ -6236,6 +6269,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"prtyw",      X(31,154),    XRB_MASK, POWER6|PPCA2|PPC476, 0,         {RA, RS}},
 
 {"brw",                X(31,155),      XRB_MASK,    POWER10,   0,              {RA, RS}},
+{"pdepd",      X(31,156),      X_MASK,      POWER10,   0,              {RA, RS, RB}},
 
 {"stdepx",     X(31,157),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
@@ -6250,6 +6284,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"addex",      ZRC(31,170,0),  Z2_MASK,     POWER9,    0,              {RT, RA, RB, CY}},
 
+{"stxvrhx",    X(31,173),      XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"msgclrp",    XRTRA(31,174,0,0), XRTRA_MASK, POWER8,  0,              {RB}},
 {"dcbtlse",    X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
 
@@ -6278,6 +6314,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"prtyd",      X(31,186),      XRB_MASK, POWER6|PPCA2, 0,              {RA, RS}},
 
 {"brd",                X(31,187),      XRB_MASK,    POWER10,   0,              {RA, RS}},
+{"pextd",      X(31,188),      X_MASK,      POWER10,   0,              {RA, RS, RB}},
 
 {"cmprb",      X(31,192),      XCMP_MASK,   POWER9,    0,              {BF, L, RA, RB}},
 
@@ -6296,6 +6333,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addze.",     XO(31,202,0,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
 {"aze.",       XO(31,202,0,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
+{"stxvrwx",    X(31,205),      XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0,  {RB}},
 
 {"mtsr",       X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
@@ -6318,6 +6357,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sleq.",      XRC(31,217,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
 {"brh",                X(31,219),      XRB_MASK,    POWER10,   0,              {RA, RS}},
+{"cfuged",     X(31,220),      X_MASK,      POWER10,   0,              {RA, RS, RB}},
 
 {"stbepx",     X(31,223),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
@@ -6346,6 +6386,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mullw.",     XO(31,235,0,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
 {"muls.",      XO(31,235,0,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
+{"stxvrdx",    X(31,237),      XX1_MASK,    POWER10,   0,              {XT6, RA0, RB}},
+
 {"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
 {"msgclr",     XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0,  {RB}},
 {"mtsrin",     X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
@@ -6754,6 +6796,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"popcntw",    X(31,378),      XRB_MASK,    POWER7|PPCA2, 0,           {RA, RS}},
 
+{"setbc",      X(31,384),      XRB_MASK,    POWER10,   0,              {RT, BI}},
+
 {"mtdcrx",     X(31,387),      X_MASK,      BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
 {"mtdcrx.",    XRC(31,387,1),  X_MASK,      PPCA2,     0,              {RA, RS}},
 
@@ -6788,6 +6832,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"sthepx",     X(31,415),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
+{"setbcr",     X(31,416),      XRB_MASK,    POWER10,   0,              {RT, BI}},
+
 {"mtdcrux",    X(31,419),      X_MASK,  PPC464|PPC476, 0,              {RA, RS}},
 
 {"stvexhx",    X(31,421),      X_MASK,      E6500,     0,              {VS, RA0, RB}},
@@ -6825,6 +6871,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mr.",                XRC(31,444,1),  X_MASK,      COM,       0,              {RA, RSB}},
 {"or.",                XRC(31,444,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
 
+{"setnbc",     X(31,448),      XRB_MASK,    POWER10,   0,              {RT, BI}},
+
 {"mtexisr",    XSPR(31,451, 64), XSPR_MASK, PPC403,    0,              {RS}},
 {"mtexier",    XSPR(31,451, 66), XSPR_MASK, PPC403,    0,              {RS}},
 {"mtbr0",      XSPR(31,451,128), XSPR_MASK, PPC403,    0,              {RS}},
@@ -7067,6 +7115,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nand",       XRC(31,476,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
 {"nand.",      XRC(31,476,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
 
+{"setnbcr",    X(31,480),      XRB_MASK,    POWER10,   0,              {RT, BI}},
+
 {"dsn",                X(31,483),      XRT_MASK,    E500MC,    0,              {RA, RB}},
 
 {"dcread",     X(31,486),      X_MASK,  PPC403|PPC440, PPCA2,          {RT, RA0, RB}},
@@ -7170,6 +7220,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cnttzd",     XRC(31,570,0),  XRB_MASK,    POWER9,    0,              {RA, RS}},
 {"cnttzd.",    XRC(31,570,1),  XRB_MASK,    POWER9,    0,              {RA, RS}},
 
+{"cnttzdm",    X(31,571),      X_MASK,      POWER10,   0,              {RA, RS, RB}},
+
 {"mcrxrx",     X(31,576),     XBFRARB_MASK, POWER9,    0,              {BF}},
 
 {"lwdcbx",     X(31,578),      X_MASK,      E200Z4,    0,              {RT, RA, RB}},
@@ -8049,6 +8101,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xxgenpcvdm", X(60,949),      XX1_MASK,    POWER10,   PPCVLE,         {XT6, VB, UIMM}},
 {"xvxexpdp",   XX2VA(60,475,0),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
 {"xvxsigdp",   XX2VA(60,475,1),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvtlsbb",    XX2VA(60,475,2),XX2BF_MASK,  POWER10,   PPCVLE,         {OBF, XB6}},
 {"xxbrh",      XX2VA(60,475,7),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
 {"xvxexpsp",   XX2VA(60,475,8),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
 {"xvxsigsp",   XX2VA(60,475,9),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
@@ -8198,6 +8251,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dquaiq",     ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6,   PPCVLE,         {TE, FRTp, FRBp, RMC}},
 {"dquaiq.",    ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6,   PPCVLE,         {TE, FRTp, FRBp, RMC}},
 
+{"xscmpeqqp",  X(63,68),       X_MASK,      POWER10,   PPCVLE,         {VD, VA, VB}},
+
 {"mtfsb0",     XRC(63,70,0),   XRARB_MASK,  COM,       PPCVLE,         {BTF}},
 {"mtfsb0.",    XRC(63,70,1),   XRARB_MASK,  COM,       PPCVLE,         {BTF}},
 
@@ -8238,11 +8293,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xscmpexpqp", X(63,164),      XBF_MASK,    PPCVSX3,   PPCVLE,         {BF, VA, VB}},
 
 {"dtstdcq",    Z(63,194),      Z_MASK,      POWER6,    PPCVLE,         {BF, FRAp, DCM}},
+
+{"xscmpgeqp",  X(63,196),      X_MASK,      POWER10,   PPCVLE,         {VD, VA, VB}},
+
 {"dtstdgq",    Z(63,226),      Z_MASK,      POWER6,    PPCVLE,         {BF, FRAp, DGM}},
 
 {"drintnq",    ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6,  PPCVLE,         {R, FRTp, FRBp, RMC}},
 {"drintnq.",   ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6,  PPCVLE,         {R, FRTp, FRBp, RMC}},
 
+{"xscmpgtqp",  X(63,228),      X_MASK,      POWER10,   PPCVLE,         {VD, VA, VB}},
+
 {"dctqpq",     XRC(63,258,0), X_MASK|Q_MASK, POWER6,   PPCVLE,         {FRTp, FRB}},
 {"dctqpq.",    XRC(63,258,1), X_MASK|Q_MASK, POWER6,   PPCVLE,         {FRTp, FRB}},
 
@@ -8311,6 +8371,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dtstsfq",    X(63,674),      X_MASK,      POWER6,    PPCVLE,         {BF, FRA, FRBp}},
 {"dtstsfiq",   X(63,675),      X_MASK|1<<22,POWER9,    PPCVLE,         {BF, UIM6, FRBp}},
 
+{"xsmaxcqp",   X(63,676),      X_MASK,      POWER10,   PPCVLE,         {VD, VA, VB}},
+
 {"xststdcqp",  X(63,708),      X_MASK,      PPCVSX3,   PPCVLE,         {BF, VB, DCMX}},
 
 {"mtfsf",      XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE,  {FLM, FRB, XFL_L, W}},
@@ -8318,6 +8380,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtfsf.",     XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE,  {FLM, FRB, XFL_L, W}},
 {"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
 
+{"xsmincqp",   X(63,740),      X_MASK,      POWER10,   PPCVLE,         {VD, VA, VB}},
+
 {"drdpq",      XRC(63,770,0), X_MASK|Q_MASK, POWER6,   PPCVLE,         {FRTp, FRBp}},
 {"drdpq.",     XRC(63,770,1), X_MASK|Q_MASK, POWER6,   PPCVLE,         {FRTp, FRBp}},
 
@@ -8408,6 +8472,7 @@ const struct powerpc_opcode prefix_opcodes[] = {
 {"xxblendvw",    P8RR|XX4(33,2),      P_XX4_MASK,      POWER10, 0,     {XT6, XA6, XB6, XC6}},
 {"xxblendvd",    P8RR|XX4(33,3),      P_XX4_MASK,      POWER10, 0,     {XT6, XA6, XB6, XC6}},
 {"xxpermx",      P8RR|XX4(34,0),      P_UXX4_MASK,     POWER10, 0,     {XT6, XA6, XB6, XC6, UIM3}},
+{"xxeval",       P8RR|XX4(34,1),      P_U8XX4_MASK,    POWER10, 0,     {XT6, XA6, XB6, XC6, UIM8}},
 {"plbz",         PMLS|OP(34),         P_D_MASK,        POWER10, 0,     {RT, D34, PRA0, PCREL}},
 {"pstw",         PMLS|OP(36),         P_D_MASK,        POWER10, 0,     {RS, D34, PRA0, PCREL}},
 {"pstb",         PMLS|OP(38),         P_D_MASK,        POWER10, 0,     {RS, D34, PRA0, PCREL}},