* ppc-opc.c (BH, XLBH_MASK): Define.

[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index e9df5ded393de115b8d8cffa4cac02ad12913c40..f5ff9baf0d4aca291bf38fe741bda731ac065bfb 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -194,8 +194,11 @@ const struct powerpc_operand powerpc_operands[] =
 #define BOE BO + 1
   { 5, 21, insert_boe, extract_boe, 0 },
 
+#define BH BOE + 1
+  { 2, 11, 0, 0, PPC_OPERAND_OPTIONAL },
+
   /* The BT field in an X or XL form instruction.  */
-#define BT BOE + 1
+#define BT BH + 1
   { 5, 21, 0, 0, PPC_OPERAND_CR },
 
   /* The condition register number portion of the BI field in a B form
@@ -1004,8 +1007,13 @@ insert_fxm (unsigned long insn,
 
   /* If only one bit of the FXM field is set, we can use the new form
      of the instruction, which is faster.  Unlike the Power4 branch hint
-     encoding, this is not backward compatible.  */
-  else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
+     encoding, this is not backward compatible.  Do not generate the
+     new form unless -mpower4 has been given, or -many and the two
+     operand form of mfcr was used.  */
+  else if ((value & -value) == value
+          && ((dialect & PPC_OPCODE_POWER4) != 0
+              || ((dialect & PPC_OPCODE_ANY) != 0
+                  && (insn & (0x3ff << 1)) == 19 << 1)))
     insn |= 1 << 20;
 
   /* Any other value on mfcr is an error.  */
@@ -1591,8 +1599,9 @@ extract_tbr (unsigned long insn,
 /* The mask for an X form comparison instruction.  */
 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
 
-/* The mask for an X form instruction with the L field fixed.  */
-#define XOPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
+/* The mask for an X form comparison instruction with the L field
+   fixed.  */
+#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
 
 /* An X form trap instruction with the TO field specified.  */
 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
@@ -1650,6 +1659,9 @@ extract_tbr (unsigned long insn,
 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
 
+/* A mask for branch instructions using the BH field.  */
+#define XLBH_MASK (XL_MASK | (0x1c << 11))
+
 /* An XL_MASK with the BO and BB fields fixed.  */
 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
 
@@ -1763,7 +1775,7 @@ extract_tbr (unsigned long insn,
 #define PPC440 PPC_OPCODE_440
 #define PPC750 PPC
 #define PPC860 PPC
-#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
+#define PPCVEC PPC_OPCODE_ALTIVEC
 #define        POWER   PPC_OPCODE_POWER
 #define        POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
 #define PPCPWR2        PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
@@ -2877,12 +2889,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4,        { BI } },
 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bclr",    XLLK(19,16,0), XLYBB_MASK,        PPCCOM,         { BO, BI } },
-{ "bclrl",   XLLK(19,16,1), XLYBB_MASK,        PPCCOM,         { BO, BI } },
 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
+{ "bclr",    XLLK(19,16,0), XLBH_MASK, PPCCOM,         { BO, BI, BH } },
+{ "bclrl",   XLLK(19,16,1), XLBH_MASK, PPCCOM,         { BO, BI, BH } },
 { "bcr",     XLLK(19,16,0), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bcrl",    XLLK(19,16,1), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bclre",   XLLK(19,17,0), XLBB_MASK, BOOKE64,        { BO, BI } },
@@ -3061,12 +3073,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,  { BO, BI } },
 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
-{ "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,  { BO, BI } },
 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
+{ "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,  { BO, BI, BH } },
+{ "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,  { BO, BI, BH } },
 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64, { BO, BI } },
@@ -3145,10 +3157,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "rldcr",   MDS(30,9,0), MDS_MASK,    PPC64,          { RA, RS, RB, ME6 } },
 { "rldcr.",  MDS(30,9,1), MDS_MASK,    PPC64,          { RA, RS, RB, ME6 } },
 
-{ "cmpw",    XOPL(31,0,0), XOPL_MASK, PPCCOM,          { OBF, RA, RB } },
-{ "cmpd",    XOPL(31,0,1), XOPL_MASK, PPC64,           { OBF, RA, RB } },
+{ "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
+{ "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
 { "cmp",     X(31,0),  XCMP_MASK,      PPC,            { BF, L, RA, RB } },
-{ "cmp",     X(31,0),  XOPL_MASK,      PWRCOM,         { BF, RA, RB } },
+{ "cmp",     X(31,0),  XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
 
 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,                { RA, RB } },
 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,                { RA, RB } },
@@ -3251,10 +3263,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lwzxe",   X(31,31), X_MASK,         BOOKE64,        { RT, RA0, RB } },
 
-{ "cmplw",   XOPL(31,32,0), XOPL_MASK, PPCCOM, { OBF, RA, RB } },
-{ "cmpld",   XOPL(31,32,1), XOPL_MASK, PPC64,          { OBF, RA, RB } },
+{ "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
+{ "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
 { "cmpl",    X(31,32), XCMP_MASK,       PPC,           { BF, L, RA, RB } },
-{ "cmpl",    X(31,32), XOPL_MASK,       PWRCOM,        { BF, RA, RB } },
+{ "cmpl",    X(31,32), XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
 
 { "subf",    XO(31,40,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "sub",     XO(31,40,0,0), XO_MASK,   PPC,            { RT, RB, RA } },