/* RISC-V disassembler
- Copyright (C) 2011-2018 Free Software Foundation, Inc.
+ Copyright (C) 2011-2021 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
#include "opintl.h"
#include "elf-bfd.h"
#include "elf/riscv.h"
+#include "cpu-riscv.h"
#include <stdint.h>
#include <ctype.h>
+static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
+
struct riscv_private_data
{
bfd_vma gp;
static const char * const *riscv_gpr_names;
static const char * const *riscv_fpr_names;
-/* Other options. */
-static int no_aliases; /* If set disassemble as most general inst. */
+/* If set, disassemble as most general instruction. */
+static int no_aliases;
static void
set_default_riscv_dis_options (void)
no_aliases = 0;
}
-static void
-parse_riscv_dis_option (const char *option)
+static bool
+parse_riscv_dis_option_without_args (const char *option)
{
if (strcmp (option, "no-aliases") == 0)
no_aliases = 1;
riscv_fpr_names = riscv_fpr_names_numeric;
}
else
+ return false;
+ return true;
+}
+
+static void
+parse_riscv_dis_option (const char *option)
+{
+ char *equal, *value;
+
+ if (parse_riscv_dis_option_without_args (option))
+ return;
+
+ equal = strchr (option, '=');
+ if (equal == NULL)
{
- /* Invalid option. */
- fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
+ /* The option without '=' should be defined above. */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
+ return;
+ }
+ if (equal == option
+ || *(equal + 1) == '\0')
+ {
+ /* Invalid options with '=', no option name before '=',
+ and no value after '='. */
+ opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
+ option);
+ return;
+ }
+
+ *equal = '\0';
+ value = equal + 1;
+ if (strcmp (option, "priv-spec") == 0)
+ {
+ enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
+ const char *name = NULL;
+
+ RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec);
+ if (priv_spec == PRIV_SPEC_CLASS_NONE)
+ opcodes_error_handler (_("unknown privileged spec set by %s=%s"),
+ option, value);
+ else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
+ default_priv_spec = priv_spec;
+ else if (default_priv_spec != priv_spec)
+ {
+ RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec);
+ opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
+ "the elf privilege attribute is %s"),
+ option, value, name);
+ }
+ }
+ else
+ {
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
}
}
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
- pd->print_addr = pd->hi_addr[base_reg] + offset;
+ pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
pd->hi_addr[base_reg] = -1;
}
else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
case 'C': /* RVC */
switch (*++d)
{
- case 's': /* RS1 x8-x15 */
- case 'w': /* RS1 x8-x15 */
+ case 's': /* RS1 x8-x15. */
+ case 'w': /* RS1 x8-x15. */
print (info->stream, "%s",
riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
break;
- case 't': /* RS2 x8-x15 */
- case 'x': /* RS2 x8-x15 */
+ case 't': /* RS2 x8-x15. */
+ case 'x': /* RS2 x8-x15. */
print (info->stream, "%s",
riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
break;
- case 'U': /* RS1, constrained to equal RD */
+ case 'U': /* RS1, constrained to equal RD. */
print (info->stream, "%s", riscv_gpr_names[rd]);
break;
- case 'c': /* RS1, constrained to equal sp */
+ case 'c': /* RS1, constrained to equal sp. */
print (info->stream, "%s", riscv_gpr_names[X_SP]);
break;
case 'V': /* RS2 */
print (info->stream, "%s",
riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
break;
- case 'i':
- print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
- break;
case 'o':
case 'j':
- print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l));
break;
case 'k':
- print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CLTYPE_LW_IMM (l));
break;
case 'l':
- print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CLTYPE_LD_IMM (l));
break;
case 'm':
- print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CITYPE_LWSP_IMM (l));
break;
case 'n':
- print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CITYPE_LDSP_IMM (l));
break;
case 'K':
- print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l));
break;
case 'L':
- print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CITYPE_ADDI16SP_IMM (l));
break;
case 'M':
- print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SWSP_IMM (l));
break;
case 'N':
- print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SDSP_IMM (l));
break;
case 'p':
- info->target = EXTRACT_RVC_B_IMM (l) + pc;
+ info->target = EXTRACT_CBTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
break;
case 'a':
- info->target = EXTRACT_RVC_J_IMM (l) + pc;
+ info->target = EXTRACT_CJTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
break;
case 'u':
print (info->stream, "0x%x",
- (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
+ (int)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1)));
break;
case '>':
- print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
+ print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x3f);
break;
case '<':
- print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
+ print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x1f);
break;
- case 'T': /* floating-point RS2 */
+ case 'T': /* Floating-point RS2. */
print (info->stream, "%s",
riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
break;
- case 'D': /* floating-point RS2 x8-x15 */
+ case 'D': /* Floating-point RS2 x8-x15. */
print (info->stream, "%s",
riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
break;
break;
case '0':
- /* Only print constant 0 if it is the last argument */
+ /* Only print constant 0 if it is the last argument. */
if (!d[1])
print (info->stream, "0");
break;
case 'b':
case 's':
+ if ((l & MASK_JALR) == MATCH_JALR)
+ maybe_print_address (pd, rs1, 0);
print (info->stream, "%s", riscv_gpr_names[rs1]);
break;
break;
case 'a':
- info->target = EXTRACT_UJTYPE_IMM (l) + pc;
+ info->target = EXTRACT_JTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
break;
case 'p':
- info->target = EXTRACT_SBTYPE_IMM (l) + pc;
+ info->target = EXTRACT_BTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
break;
else if ((l & MASK_LUI) == MATCH_LUI)
pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
else if ((l & MASK_C_LUI) == MATCH_C_LUI)
- pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
+ pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l);
print (info->stream, "%s", riscv_gpr_names[rd]);
break;
case 'E':
{
- const char* csr_name = NULL;
+ static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */
+ static bool init_csr = false;
unsigned int csr = EXTRACT_OPERAND (CSR, l);
- switch (csr)
+
+ if (!init_csr)
{
-#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
+ unsigned int i;
+ for (i = 0; i < 4096; i++)
+ riscv_csr_hash[i] = NULL;
+
+ /* Set to the newest privileged version. */
+ if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
+ default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
+
+#define DECLARE_CSR(name, num, class, define_version, abort_version) \
+ if (riscv_csr_hash[num] == NULL \
+ && ((define_version == PRIV_SPEC_CLASS_NONE \
+ && abort_version == PRIV_SPEC_CLASS_NONE) \
+ || (default_priv_spec >= define_version \
+ && default_priv_spec < abort_version))) \
+ riscv_csr_hash[num] = #name;
+#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
+ DECLARE_CSR (name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
- if (csr_name)
- print (info->stream, "%s", csr_name);
+
+ if (riscv_csr_hash[csr] != NULL)
+ print (info->stream, "%s", riscv_csr_hash[csr]);
else
print (info->stream, "0x%x", csr);
break;
riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
{
const struct riscv_opcode *op;
- static bfd_boolean init = 0;
+ static bool init = 0;
static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
struct riscv_private_data *pd;
int insnlen;
insnlen = riscv_insn_length (word);
+ /* RISC-V instructions are always little-endian. */
+ info->endian_code = BFD_ENDIAN_LITTLE;
+
info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
info->bytes_per_line = 8;
- info->display_endian = info->endian;
+ /* We don't support constant pools, so this must be code. */
+ info->display_endian = info->endian_code;
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
info->data_size = 0;
op = riscv_hash[OP_HASH_IDX (word)];
if (op != NULL)
{
- int xlen = 0;
+ unsigned xlen = 0;
/* If XLEN is not known, get its value from the ELF class. */
if (info->mach == bfd_mach_riscv64)
if (no_aliases && (op->pinfo & INSN_ALIAS))
continue;
/* Is this instruction restricted to a certain value of XLEN? */
- if (isdigit (op->subset[0]) && atoi (op->subset) != xlen)
+ if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
continue;
/* It's a match. */
pd->print_addr = -1;
}
+ /* Finish filling out insn_info fields. */
+ switch (op->pinfo & INSN_TYPE)
+ {
+ case INSN_BRANCH:
+ info->insn_type = dis_branch;
+ break;
+ case INSN_CONDBRANCH:
+ info->insn_type = dis_condbranch;
+ break;
+ case INSN_JSR:
+ info->insn_type = dis_jsr;
+ break;
+ case INSN_DREF:
+ info->insn_type = dis_dref;
+ break;
+ default:
+ break;
+ }
+
+ if (op->pinfo & INSN_DATA_SIZE)
+ {
+ int size = ((op->pinfo & INSN_DATA_SIZE)
+ >> INSN_DATA_SIZE_SHIFT);
+ info->data_size = 1 << (size - 1);
+ }
+
return insnlen;
}
}
return riscv_disassemble_insn (memaddr, insn, info);
}
+disassembler_ftype
+riscv_get_disassembler (bfd *abfd)
+{
+ if (abfd)
+ {
+ const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
+ if (bfd_get_section_by_name (abfd, sec_name) != NULL)
+ {
+ obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
+ unsigned int Tag_a = Tag_RISCV_priv_spec;
+ unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
+ unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
+ riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
+ attr[Tag_b].i,
+ attr[Tag_c].i,
+ &default_priv_spec);
+ }
+ }
+ return print_insn_riscv;
+}
+
+/* Prevent use of the fake labels that are generated as part of the DWARF
+ and for relaxable relocations in the assembler. */
+
+bool
+riscv_symbol_is_valid (asymbol * sym,
+ struct disassemble_info * info ATTRIBUTE_UNUSED)
+{
+ const char * name;
+
+ if (sym == NULL)
+ return false;
+
+ name = bfd_asymbol_name (sym);
+
+ return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
+}
+
void
print_riscv_disassembler_options (FILE *stream)
{
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
- numeric Print numeric register names, rather than ABI names.\n"));
+ numeric Print numeric register names, rather than ABI names.\n"));
+
+ fprintf (stream, _("\n\
+ no-aliases Disassemble only into canonical instructions, rather\n\
+ than into pseudoinstructions.\n"));
fprintf (stream, _("\n\
- no-aliases Disassemble only into canonical instructions, rather\n\
- than into pseudoinstructions.\n"));
+ priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
+ (1.9, 1.9.1, 1.10, 1.11).\n"));
fprintf (stream, _("\n"));
}
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