RISC-V: Add compressed instruction hints, and a few misc cleanups.

[deliverable/binutils-gdb.git] / opcodes / riscv-dis.c

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d701d49a43eabeae1359794e508ce842c898..17d042afb5bb5ba0531b99308ebafedfac261af6 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -21,7 +21,7 @@
    see <http://www.gnu.org/licenses/>.  */
 
 #include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
 #include "libiberty.h"
 #include "opcode/riscv.h"
 #include "opintl.h"
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
            case 'i':
              print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
              break;
+           case 'o':
            case 'j':
              print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
              break;
@@ -497,7 +498,7 @@ The following RISC-V-specific disassembler options are supported for use\n\
 with the -M switch (multiple options should be separated by commas):\n"));
 
   fprintf (stream, _("\n\
-  numeric       Print numeric reigster names, rather than ABI names.\n"));
+  numeric       Print numeric register names, rather than ABI names.\n"));
 
   fprintf (stream, _("\n\
   no-aliases    Disassemble only into canonical instructions, rather\n\