RISC-V: Fix disassemble for c.li, c.andi and c.addiw

[deliverable/binutils-gdb.git] / opcodes / riscv-dis.c

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d701d49a43eabeae1359794e508ce842c898..bb534633102c3274f1b3a2b0fdc14370497defea 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
            case 'i':
              print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
              break;
+           case 'o':
            case 'j':
              print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
              break;