Enable Intel AVX512_4FMAPS instructions

[deliverable/binutils-gdb.git] / opcodes / rl78-decode.opc

diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc
index 28362c1ebfb81143e4cfe8606ba98574e555bdd3..57e79ed1de48ea5d16a1160126d0123711efd526 100644 (file)
--- a/opcodes/rl78-decode.opc
+++ b/opcodes/rl78-decode.opc
@@ -1,5 +1,5 @@
 /* -*- c -*- */
-/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
+/* Copyright (C) 2012-2016 Free Software Foundation, Inc.
    Contributed by Red Hat.
    Written by DJ Delorie.
 
@@ -614,10 +614,10 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1001 1001                  mov     %e0, %1                         */
   ID(mov); DM(DE, 0); SR(A);
 
-/** 1100 1010                  mov     %e0, #%1                        */
+/** 1100 1010                  mov     %ea0, #%1                       */
   ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
 
-/** 1001 1010                  mov     %e0, %1                         */
+/** 1001 1010                  mov     %ea0, %1                                */
   ID(mov); DM(DE, IMMU(1)); SR(A);
 
 /** 1001 1011                  mov     %e0, %1                         */
@@ -647,7 +647,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1000 1001                  mov     %0, %e1                         */
   ID(mov); DR(A); SM(DE, 0);
 
-/** 1000 1010                  mov     %0, %e1                         */
+/** 1000 1010                  mov     %0, %ea1                        */
   ID(mov); DR(A); SM(DE, IMMU(1));
 
 /** 1000 1011                  mov     %0, %e1                         */
@@ -818,7 +818,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1011 1001                  movw    %e0, %1                         */
   ID(mov); W(); DM(DE, 0); SR(AX);
 
-/** 1011 1010                  movw    %e0, %1                         */
+/** 1011 1010                  movw    %ea0, %1                                */
   ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
 
 /** 1011 1011                  movw    %e0, %1                         */
@@ -837,7 +837,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1010 1001                  movw    %0, %e1                         */
   ID(mov); W(); DR(AX); SM(DE, 0);
 
-/** 1010 1010                  movw    %0, %e1                         */
+/** 1010 1010                  movw    %0, %ea1                                */
   ID(mov); W(); DR(AX); SM(DE, IMMU(1));
 
 /** 1010 1011                  movw    %0, %e1                         */
@@ -882,7 +882,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 1010 1110                  movw    %0, %s1                         */
   ID(mov); W(); DR(AX); SM(None, SFR);
 
-/** 11ra 1011                  movw    %0, %e!1                        */
+/** 11ra 1011                  movw    %0, %es!1                       */
   ID(mov); W(); DRW(ra); SM(None, IMMU(2));
 
 /** 11ra 1010                  movw    %0, %1                          */
@@ -903,8 +903,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /*----------------------------------------------------------------------*/
 
 /** 1101 0110                  mulu    x                               */
-  if (isa == RL78_ISA_G14)
-    ID(mulu);
+  ID(mulu);
 
 /*----------------------------------------------------------------------*/
 
@@ -1206,7 +1205,7 @@ rl78_decode_opcode (unsigned long pc AU,
 /** 0110 0001 1010 1110                xch     %0, %e1                         */
   ID(xch); DR(A); SM(DE, 0);
 
-/** 0110 0001 1010 1111                xch     %0, %e1                         */
+/** 0110 0001 1010 1111                xch     %0, %ea1                                */
   ID(xch); DR(A); SM(DE, IMMU(1));
 
 /** 0110 0001 1010 1100                xch     %0, %e1                         */