arc/opcodes/nps400: Fix some instruction masks

[deliverable/binutils-gdb.git] / opcodes / rl78-dis.c

diff --git a/opcodes/rl78-dis.c b/opcodes/rl78-dis.c
index 6784e53a30c3c9b43b5654ea3d56c32220c8f6f3..a23999dc3a1c0119fdb4afb337232aea437e5c89 100644 (file)
--- a/opcodes/rl78-dis.c
+++ b/opcodes/rl78-dis.c
@@ -229,7 +229,8 @@ print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
            if (do_bang)
              {
                /* If we are going to display SP by name, we must omit the bang.  */
-               if ((oper->type == RL78_Operand_Indirect || RL78_Operand_BitIndirect)
+               if ((oper->type == RL78_Operand_Indirect
+                    || oper->type == RL78_Operand_BitIndirect)
                    && oper->reg == RL78_Reg_None
                    && do_sfr
                    && ((oper->addend == 0xffff8 && opcode.size == RL78_Word)