[AArch64] Add SVE condition codes

[deliverable/binutils-gdb.git] / opcodes / rx-dis.c

diff --git a/opcodes/rx-dis.c b/opcodes/rx-dis.c
index cab0385d3c3d3770d12e6fa862784d5c11b8b718..b0ff4b36974b4bc1e87af0bb63754cd6217e38c5 100644 (file)
--- a/opcodes/rx-dis.c
+++ b/opcodes/rx-dis.c
@@ -1,5 +1,5 @@
 /* Disassembler code for Renesas RX.
-   Copyright (C) 2008-2015 Free Software Foundation, Inc.
+   Copyright (C) 2008-2016 Free Software Foundation, Inc.
    Contributed by Red Hat.
    Written by DJ Delorie.
 
@@ -65,16 +65,16 @@ static char const * register_names[] =
   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
   /* control register */
   "psw", "pc", "usp", "fpsw", NULL, NULL, NULL, NULL,
-  "bpsw", "bpc", "isp", "fintv", "intb", NULL, NULL, NULL,
+  "bpsw", "bpc", "isp", "fintv", "intb", "extb", NULL, NULL,
+  "a0", "a1", NULL, NULL, NULL, NULL, NULL, NULL,
   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
 };
 
 static char const * condition_names[] =
 {
   /* condition codes */
   "eq", "ne", "c", "nc", "gtu", "leu", "pz", "n",
-  "ge", "lt", "gt", "le", "o", "no", "always", "never"
+  "ge", "lt", "gt", "le", "o", "no", "<invalid>", "<invalid>"
 };
 
 static const char * flag_names[] =
@@ -168,7 +168,7 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis)
              oper = opcode.op + *s - '0';
              if (do_size)
                {
-                 if (oper->type == RX_Operand_Indirect)
+                 if (oper->type == RX_Operand_Indirect || oper->type == RX_Operand_Zero_Indirect)
                    PR (PS, "%s", size_names[oper->size]);
                }
              else
@@ -189,10 +189,10 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis)
                    PR (PS, "%s", register_names[oper->reg]);
                    break;
                  case RX_Operand_Indirect:
-                   if (oper->addend)
-                     PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
-                   else
-                     PR (PS, "[%s]", register_names[oper->reg]);
+                   PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
+                   break;
+                 case RX_Operand_Zero_Indirect:
+                   PR (PS, "[%s]", register_names[oper->reg]);
                    break;
                  case RX_Operand_Postinc:
                    PR (PS, "[%s+]", register_names[oper->reg]);