#include <stdbool.h>
#include <assert.h>
-#include "s12z.h"
+#include "opcode/s12z.h"
#include "bfd.h"
#include "dis-asm.h"
if (status < 0)
return;
- char *reg = NULL;
+ char *reg_xys = NULL;
switch (byte & 0x03)
{
case 0x00:
- reg = "x";
+ reg_xys = "x";
break;
case 0x01:
- reg = "y";
+ reg_xys = "y";
break;
case 0x02:
- reg = "s";
+ reg_xys = "s";
break;
}
operand_separator (info);
- (*info->fprintf_func) (info->stream, "%s", reg);
+ (*info->fprintf_func) (info->stream, "%s", reg_xys);
opr_decode (memaddr, info);
}
if (status < 0)
return;
- char *reg = NULL;
+ char *reg_xys = NULL;
switch (byte & 0x03)
{
case 0x00:
- reg = "x";
+ reg_xys = "x";
break;
case 0x01:
- reg = "y";
+ reg_xys = "y";
break;
case 0x02:
- reg = "s";
+ reg_xys = "s";
break;
}
int8_t v = byte;
operand_separator (info);
- (*info->fprintf_func) (info->stream, "%s, (%d,%s)", reg, v, reg);
+ (*info->fprintf_func) (info->stream, "%s, (%d,%s)", reg_xys, v, reg_xys);
}
}
\f
+ /* The NXP documentation is vague about BM_RESERVED0 and BM_RESERVED1,
+ and contains obvious typos.
+ However the Freescale tools and experiments with the chip itself
+ seem to indicate that they behave like BM_REG_IMM and BM_OPR_REG
+ respectively. */
+
enum BM_MODE {
BM_REG_IMM,
BM_RESERVED0,
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
operand_separator (info);
(*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
break;
opr_decode (memaddr + 1, info);
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
{
uint8_t xb;
read_memory (memaddr + 1, &xb, 1, info);
opr_decode (memaddr + 1, info);
}
break;
- case BM_RESERVED0:
- case BM_RESERVED1:
- assert (0);
- break;
}
uint8_t imm = 0;
{
case BM_REG_IMM:
{
- imm = (bm & 0xF8) >> 3;
+ imm = (bm & 0x38) >> 3;
(*info->fprintf_func) (info->stream, "#%d", imm);
}
break;
(*info->fprintf_func) (info->stream, "#%d", imm);
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
(*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
break;
case BM_RESERVED0:
- case BM_RESERVED1:
assert (0);
break;
}
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
break;
case BM_OPR_B:
(*info->fprintf_func) (info->stream, ".%c", 'b');
(*info->fprintf_func) (info->stream, ".%c", 'l');
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
{
uint8_t xb;
read_memory (memaddr + 1, &xb, 1, info);
shift_size_table[(bm & 0x0C) >> 2]);
}
break;
- case BM_RESERVED0:
- case BM_RESERVED1:
- assert (0);
- break;
}
int n = 1;
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
operand_separator (info);
(*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
break;
n = 1 + opr_n_bytes (memaddr + 1, info);
break;
case BM_OPR_REG:
- opr_decode (memaddr + 1, info);
- break;
- case BM_RESERVED0:
case BM_RESERVED1:
- assert (0);
+ opr_decode (memaddr + 1, info);
break;
}
imm |= (bm & 0x70) >> 4;
(*info->fprintf_func) (info->stream, "#%d", imm);
break;
+ case BM_RESERVED0:
+ imm = (bm & 0x38) >> 3;
+ (*info->fprintf_func) (info->stream, "#%d", imm);
+ break;
case BM_REG_IMM:
imm = (bm & 0xF8) >> 3;
(*info->fprintf_func) (info->stream, "#%d", imm);
break;
- case BM_RESERVED0:
- case BM_RESERVED1:
- assert (0);
- break;
case BM_OPR_REG:
+ case BM_RESERVED1:
(*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
n += opr_n_bytes (memaddr + 1, info);
break;
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
break;
case BM_OPR_B:
n += opr_n_bytes (memaddr + 1, info);
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
n += opr_n_bytes (memaddr + 1, info);
break;
- default:
- break;
}
return n;
stpcpy (mnemonic + x, lb_condition [(lb & 0x70) >> 4]);
x += 2;
- const char *reg = NULL;
+ const char *reg_dxy = NULL;
enum LP_MODE mode = -1;
size_t i;
for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i)
switch (mode)
{
case LP_REG:
- reg = registers [lb & 0x07].name;
+ reg_dxy = registers [lb & 0x07].name;
break;
case LP_XY:
- reg = (lb & 0x1) ? "y" : "x";
+ reg_dxy = (lb & 0x1) ? "y" : "x";
break;
case LP_OPR:
mnemonic[x++] = '.';
else
{
operand_separator (info);
- (*info->fprintf_func) (info->stream, "%s", reg);
+ (*info->fprintf_func) (info->stream, "%s", reg_dxy);
}
rel_15_7 (memaddr + offs, info, offs + 1);