[ARM] Improve indentation of ARM architecture declarations

[deliverable/binutils-gdb.git] / opcodes / s12z-dis.c

diff --git a/opcodes/s12z-dis.c b/opcodes/s12z-dis.c
index 47f861639033df3c81c9db3f514746906445fd78..ad39e052175f1038cd0ac3b1dc1c5d6f97900c25 100644 (file)
--- a/opcodes/s12z-dis.c
+++ b/opcodes/s12z-dis.c
@@ -24,7 +24,7 @@
 #include <stdbool.h>
 #include <assert.h>
 
-#include "s12z.h"
+#include "opcode/s12z.h"
 
 #include "bfd.h"
 #include "dis-asm.h"
@@ -378,6 +378,8 @@ decode_possible_symbol (bfd_vma addr, struct disassemble_info *info)
        }
       if (j < info->symtab_size)
        (*info->fprintf_func) (info->stream, "%s", bfd_asymbol_name (sym));
+      else
+        (*info->fprintf_func) (info->stream, "%" BFD_VMA_FMT "d", addr);
     }
 }
 
@@ -922,6 +924,8 @@ rel_15_7 (bfd_vma memaddr, struct disassemble_info* info, int offset)
        }
       if (i < info->symtab_size)
        (*info->fprintf_func) (info->stream, "%s", bfd_asymbol_name (sym));
+      else
+        (*info->fprintf_func) (info->stream, "*%+d", addr);
     }
 }
 
@@ -1677,6 +1681,12 @@ mul_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
 }
 
 \f
+ /* The NXP documentation is vague about BM_RESERVED0 and BM_RESERVED1,
+    and contains obvious typos.
+    However the Freescale tools and experiments with the chip itself
+    seem to indicate that they behave like BM_REG_IMM and BM_OPR_REG
+    respectively.  */
+
 enum BM_MODE {
   BM_REG_IMM,
   BM_RESERVED0,
@@ -1731,6 +1741,7 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
   switch (mode)
     {
     case BM_REG_IMM:
+    case BM_RESERVED0:
       operand_separator (info);
       (*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
       break;
@@ -1747,6 +1758,7 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
       opr_decode (memaddr + 1, info);
       break;
     case BM_OPR_REG:
+    case BM_RESERVED1:
       {
        uint8_t xb;
        read_memory (memaddr + 1, &xb, 1, info);
@@ -1756,10 +1768,6 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
        opr_decode (memaddr + 1, info);
       }
       break;
-    case BM_RESERVED0:
-    case BM_RESERVED1:
-      assert (0);
-      break;
     }
 
   uint8_t imm = 0;
@@ -1768,7 +1776,7 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
     {
     case BM_REG_IMM:
       {
-       imm = (bm & 0xF8) >> 3;
+       imm = (bm & 0x38) >> 3;
        (*info->fprintf_func) (info->stream, "#%d", imm);
       }
       break;
@@ -1783,10 +1791,10 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
       (*info->fprintf_func) (info->stream, "#%d", imm);
       break;
     case BM_OPR_REG:
+    case BM_RESERVED1:
       (*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
       break;
     case BM_RESERVED0:
-    case BM_RESERVED1:
       assert (0);
       break;
     }
@@ -1816,6 +1824,7 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
   switch (mode)
     {
     case BM_REG_IMM:
+    case BM_RESERVED0:
       break;
     case BM_OPR_B:
       (*info->fprintf_func) (info->stream, ".%c", 'b');
@@ -1827,6 +1836,7 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
       (*info->fprintf_func) (info->stream, ".%c", 'l');
       break;
     case BM_OPR_REG:
+    case BM_RESERVED1:
       {
        uint8_t xb;
        read_memory (memaddr + 1, &xb, 1, info);
@@ -1836,16 +1846,13 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
                                 shift_size_table[(bm & 0x0C) >> 2]);
       }
       break;
-    case BM_RESERVED0:
-    case BM_RESERVED1:
-      assert (0);
-      break;
     }
 
   int n = 1;
   switch (mode)
     {
     case BM_REG_IMM:
+    case BM_RESERVED0:
       operand_separator (info);
       (*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
       break;
@@ -1856,11 +1863,8 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
       n = 1 + opr_n_bytes (memaddr + 1, info);
       break;
     case BM_OPR_REG:
-      opr_decode (memaddr + 1, info);
-      break;
-    case BM_RESERVED0:
     case BM_RESERVED1:
-      assert (0);
+      opr_decode (memaddr + 1, info);
       break;
     }
 
@@ -1879,15 +1883,16 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
       imm |= (bm & 0x70) >> 4;
       (*info->fprintf_func) (info->stream, "#%d", imm);
       break;
+    case BM_RESERVED0:
+      imm = (bm & 0x38) >> 3;
+      (*info->fprintf_func) (info->stream, "#%d", imm);
+      break;
     case BM_REG_IMM:
       imm = (bm & 0xF8) >> 3;
       (*info->fprintf_func) (info->stream, "#%d", imm);
       break;
-    case BM_RESERVED0:
-    case BM_RESERVED1:
-      assert (0);
-      break;
     case BM_OPR_REG:
+    case BM_RESERVED1:
       (*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
       n += opr_n_bytes (memaddr + 1, info);
       break;
@@ -1920,6 +1925,7 @@ bm_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
   switch (mode)
     {
     case BM_REG_IMM:
+    case BM_RESERVED0:
       break;
 
     case BM_OPR_B:
@@ -1928,10 +1934,9 @@ bm_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
       n += opr_n_bytes (memaddr + 1, info);
       break;
     case BM_OPR_REG:
+    case BM_RESERVED1:
       n += opr_n_bytes (memaddr + 1, info);
       break;
-    default:
-      break;
   }
 
   return n;