arc: Don't generate dynamic relocation for non SEC_ALLOC sections

[deliverable/binutils-gdb.git] / opcodes / s390-opc.txt

diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 7569a5675edc00f0e02e78ec443c1463b07055f6..33dbeb3824977f9bc8c073302b9f809f99293b93 100644 (file)
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1,5 +1,5 @@
 #  S/390 opcodes list. Use s390-mkopc to convert it into the opcode table.
-#  Copyright (C) 2000-2019 Free Software Foundation, Inc.
+#  Copyright (C) 2000-2020 Free Software Foundation, Inc.
 #  Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
 5a a RX_RRRD "add" g5 esa,zarch
 6a ad RX_FRRD "add normalized (long)" g5 esa,zarch
@@ -1159,7 +1159,6 @@ e70000000046 vgmb VRI_V0UU "vector generate mask byte" z13 zarch vx
 e70000001046 vgmh VRI_V0UU "vector generate mask halfword" z13 zarch vx
 e70000002046 vgmf VRI_V0UU "vector generate mask word" z13 zarch vx
 e70000003046 vgmg VRI_V0UU "vector generate mask double word" z13 zarch vx
-e70000000006 vl VRX_VRRD "vector memory load" z13 zarch vx
 e70000000056 vlr VRX_VV "vector register load" z13 zarch vx
 e70000000005 vlrep VRX_VRRDU "vector load and replicate" z13 zarch vx
 e70000000005 vlrepb VRX_VRRD "vector load and replicate byte elements" z13 zarch vx
@@ -1184,7 +1183,6 @@ e70000000004 vllezb VRX_VRRD "vector load logical byte element and zero" z13 zar
 e70000001004 vllezh VRX_VRRD "vector load logical halfword element and zero" z13 zarch vx
 e70000002004 vllezf VRX_VRRD "vector load logical word element and zero" z13 zarch vx
 e70000003004 vllezg VRX_VRRD "vector load logical double word element and zero" z13 zarch vx
-e70000000036 vlm VRS_VVRD "vector load multiple" z13 zarch vx
 e70000000007 vlbb VRX_VRRDU "vector load to block boundary" z13 zarch vx
 e70000000022 vlvg VRS_VRRDU "vector load VR element from GR" z13 zarch vx
 e70000000022 vlvgb VRS_VRRD "vector load VR byte element from GR" z13 zarch vx
@@ -1240,12 +1238,10 @@ e7000000005f vseg VRR_VV0U "vector sign extend to double word" z13 zarch vx
 e7000000005f vsegb VRR_VV "vector sign extend byte to double word" z13 zarch vx
 e7000000105f vsegh VRR_VV "vector sign extend halfword to double word" z13 zarch vx
 e7000000205f vsegf VRR_VV "vector sign extend word to double word" z13 zarch vx
-e7000000000e vst VRX_VRRD "vector store" z13 zarch vx
 e70000000008 vsteb VRX_VRRDU "vector store byte element" z13 zarch vx
 e70000000009 vsteh VRX_VRRDU "vector store halfword element" z13 zarch vx
 e7000000000b vstef VRX_VRRDU "vector store word element" z13 zarch vx
 e7000000000a vsteg VRX_VRRDU "vector store double word element" z13 zarch vx
-e7000000003e vstm VRS_VVRD "vector store multiple" z13 zarch vx
 e7000000003f vstl VRS_VRRD "vector store with length" z13 zarch vx
 e700000000d7 vuph VRR_VV0U "vector unpack high" z13 zarch vx
 e700000000d7 vuphb VRR_VV "vector unpack high byte" z13 zarch vx
@@ -1680,6 +1676,13 @@ e3000000003b lzrf RXY_RRRD "load and zero rightmost byte 32->32" z13 zarch
 e3000000002a lzrg RXY_RRRD "load and zero rightmost byte 64->64" z13 zarch
 b93c ppno RRE_RR "perform pseudorandom number operation" z13 zarch
 
+# Aligned vector store hints
+
+e70000000006 vl VRX_VRRDU "vector memory load" z13 zarch optparm,vx
+e70000000036 vlm VRS_VVRDU "vector load multiple" z13 zarch optparm,vx
+e7000000000e vst VRX_VRRDU "vector store" z13 zarch optparm,vx
+e7000000003e vstm VRS_VVRDU "vector store multiple" z13 zarch optparm,vx
+
 # arch12 instructions
 
 # Vector Enhancements Facility 1
@@ -1881,14 +1884,6 @@ b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch
 b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch
 b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch
 
-# Aligned vector store hints
-
-e70000000006 vl VRX_VRRDU "vector memory load" arch12 zarch optparm
-e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
-e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
-e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm
-
-
 # arch13 instructions