[ARM] Support for ARMv8.1 Adv.SIMD extension

[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c

diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index 38b76f7f7e4f0eb685f012d4d8e3b13c93a79a45..2c762567fda5a03ed3f9dff7c9a81a5974f49761 100644 (file)
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -1,5 +1,5 @@
 /* Print SPARC instructions.
-   Copyright (C) 1989-2014 Free Software Foundation, Inc.
+   Copyright (C) 1989-2015 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -97,7 +97,7 @@ static char *v9_hpriv_reg_names[] =
   "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", 
   "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
   "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
-  "resv28", "resv29", "resv30", "hstick_cmpr"
+  "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
 };
 
 /* These are ordered according to there register number in
@@ -106,7 +106,7 @@ static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
   "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
-  "pause", "cps"
+  "pause", "mwait"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
@@ -656,6 +656,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    break;
                  case 'H':     /* Double/even.  */
                  case 'J':     /* Quad/multiple of 4.  */
+                 case '}':     /* Double/even.  */
                    fregx (X_RD (insn));
                    break;
 #undef freg
@@ -793,6 +794,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    (*info->fprintf_func) (stream, "%%fprs");
                    break;
 
+                 case '{':
+                   (*info->fprintf_func) (stream, "%%mcdper");
+                   break;
+
                  case 'o':
                    (*info->fprintf_func) (stream, "%%asi");
                    break;