Add the endian reversing versions of load/store instructions;

[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c

diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index bfa7ea29931e78b8f74028efdb870478794e5d07..f0ee5189deae068cc257c63dfd6980caaf17ea5d 100644 (file)
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -1,25 +1,27 @@
 /* Print SPARC instructions.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2012
+   Free Software Foundation, Inc.
 
-   This program is free software; you can redistribute it and/or modify
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-#include <stdio.h>
-
 #include "sysdep.h"
+#include <stdio.h>
 #include "opcode/sparc.h"
 #include "dis-asm.h"
 #include "libiberty.h"
@@ -105,7 +107,8 @@ static char *v9_hpriv_reg_names[] =
 static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
-  "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
+  "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
+  "pause", "cps"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
@@ -116,6 +119,7 @@ static char *v9a_asr_reg_names[] =
 #define X_LDST_I(i)  (((i) >> 13) & 1)
 #define X_ASI(i)     (((i) >> 5) & 0xff)
 #define X_RS2(i)     (((i) >> 0) & 0x1f)
+#define X_RS3(i)     (((i) >> 9) & 0x1f)
 #define X_IMM(i,n)   (((i) >> 0) & ((1 << (n)) - 1))
 #define X_SIMM(i,n)  SEX (X_IMM ((i), (n)), (n))
 #define X_DISP22(i)  (((i) >> 0) & 0x3fffff)
@@ -124,6 +128,7 @@ static char *v9a_asr_reg_names[] =
 
 /* These are for v9.  */
 #define X_DISP16(i)  (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
+#define X_DISP10(i)  (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
 #define X_DISP19(i)  (((i) >> 0) & 0x7ffff)
 #define X_MEMBAR(i)  ((i) & 0x7f)
 
@@ -545,7 +550,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
              /* Can't do simple format if source and dest are different.  */
              continue;
 
-         (*info->fprintf_func) (stream, opcode->name);
+         (*info->fprintf_func) (stream, "%s", opcode->name);
 
          {
            const char *s;
@@ -631,6 +636,13 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    fregx (X_RS2 (insn));
                    break;
 
+                 case '4':
+                   freg (X_RS3 (insn));
+                   break;
+                 case '5':     /* Double/even.  */
+                   fregx (X_RS3 (insn));
+                   break;
+
                  case 'g':
                    freg (X_RD (insn));
                    break;
@@ -691,6 +703,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    }
                    break;
 
+                 case ')':     /* 5 bit unsigned immediate from RS3.  */
+                   (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
+                   break;
+
                  case 'X':     /* 5 bit unsigned immediate.  */
                  case 'Y':     /* 6 bit unsigned immediate.  */
                    {
@@ -731,6 +747,11 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                      break;
                    }
 
+                 case '=':
+                   info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
+                   (*info->print_address_func) (info->target, info);
+                   break;
+
                  case 'k':
                    info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
                    (*info->print_address_func) (info->target, info);
@@ -811,7 +832,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    break;
 
                  case '/':
-                   if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
+                   if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
                      (*info->fprintf_func) (stream, "%%reserved");
                    else
                      (*info->fprintf_func) (stream, "%%%s",
@@ -819,7 +840,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    break;
 
                  case '_':
-                   if (X_RD (insn) < 16 || X_RD (insn) > 25)
+                   if (X_RD (insn) < 16 || X_RD (insn) > 28)
                      (*info->fprintf_func) (stream, "%%reserved");
                    else
                      (*info->fprintf_func) (stream, "%%%s",
@@ -879,6 +900,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    (*info->fprintf_func) (stream, "%%fsr");
                    break;
 
+                 case '(':
+                   (*info->fprintf_func) (stream, "%%efsr");
+                   break;
+
                  case 'p':
                    (*info->fprintf_func) (stream, "%%psr");
                    break;
@@ -992,7 +1017,8 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
 
          if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
            {
-               /* FIXME -- check is_annulled flag.  */
+             /* FIXME -- check is_annulled flag.  */
+             (void) is_annulled;
              if (opcode->flags & F_UNBR)
                info->insn_type = dis_branch;
              if (opcode->flags & F_CONDBR)