[AArch64] Add SVE condition codes

[deliverable/binutils-gdb.git] / opcodes / tic30-dis.c

diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c
index 907743423c96db0fd82df68cc1b049697adc59dd..614da14774bc0abc395104feae5f3e0f14e91c71 100644 (file)
--- a/opcodes/tic30-dis.c
+++ b/opcodes/tic30-dis.c
@@ -1,5 +1,5 @@
 /* Disassembly routines for TMS320C30 architecture
-   Copyright (C) 1998-2015 Free Software Foundation, Inc.
+   Copyright (C) 1998-2016 Free Software Foundation, Inc.
    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
    This file is part of the GNU opcodes library.
@@ -669,9 +669,9 @@ print_branch (disassemble_info *info,
       if (address == 0)
        info->fprintf_func (info->stream, " <%s>", sym->name);
       else
-       info->fprintf_func (info->stream, " <%s %c %d>", sym->name,
+       info->fprintf_func (info->stream, " <%s %c %lu>", sym->name,
                            ((short) address < 0) ? '-' : '+',
-                           abs (address));
+                           address);
     }
   return 1;
 }