/* Opcode table for TI TMS320C80 (MVP).
- Copyright 1996 Free Software Foundation, Inc.
+ Copyright 1996, 1999 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
#include <stdio.h>
#include "ansidecl.h"
{ "ECOMCNTL", TIC80_OPERAND_CR | 0x33 },
{ "EIP", TIC80_OPERAND_CR | 1 },
{ "EPC", TIC80_OPERAND_CR | 0 },
- { "eq.b", TIC80_OPERAND_BITNUM | (~0 & 0x1F) },
- { "eq.f", TIC80_OPERAND_BITNUM | (~20 & 0x1F) },
- { "eq.h", TIC80_OPERAND_BITNUM | (~10 & 0x1F) },
- { "eq.w", TIC80_OPERAND_BITNUM | (~20 & 0x1F) },
+ { "eq.b", TIC80_OPERAND_BITNUM | 0 },
+ { "eq.f", TIC80_OPERAND_BITNUM | 20 },
+ { "eq.h", TIC80_OPERAND_BITNUM | 10 },
+ { "eq.w", TIC80_OPERAND_BITNUM | 20 },
{ "eq0.b", TIC80_OPERAND_CC | 2 },
{ "eq0.h", TIC80_OPERAND_CC | 10 },
{ "eq0.w", TIC80_OPERAND_CC | 18 },
{ "FLTOP", TIC80_OPERAND_CR | 0x10 },
{ "FLTTAG", TIC80_OPERAND_CR | 0x12 },
{ "FPST", TIC80_OPERAND_CR | 8 },
- { "ge.b", TIC80_OPERAND_BITNUM | (~5 & 0x1F) },
- { "ge.f", TIC80_OPERAND_BITNUM | (~25 & 0x1F) },
- { "ge.h", TIC80_OPERAND_BITNUM | (~15 & 0x1F) },
- { "ge.w", TIC80_OPERAND_BITNUM | (~25 & 0x1F) },
+ { "ge.b", TIC80_OPERAND_BITNUM | 5 },
+ { "ge.f", TIC80_OPERAND_BITNUM | 25 },
+ { "ge.h", TIC80_OPERAND_BITNUM | 15 },
+ { "ge.w", TIC80_OPERAND_BITNUM | 25 },
{ "ge0.b", TIC80_OPERAND_CC | 3 },
{ "ge0.h", TIC80_OPERAND_CC | 11 },
{ "ge0.w", TIC80_OPERAND_CC | 19 },
- { "gt.b", TIC80_OPERAND_BITNUM | (~2 & 0x1F) },
- { "gt.f", TIC80_OPERAND_BITNUM | (~22 & 0x1F) },
- { "gt.h", TIC80_OPERAND_BITNUM | (~12 & 0x1F) },
- { "gt.w", TIC80_OPERAND_BITNUM | (~22 & 0x1F) },
+ { "gt.b", TIC80_OPERAND_BITNUM | 2 },
+ { "gt.f", TIC80_OPERAND_BITNUM | 22 },
+ { "gt.h", TIC80_OPERAND_BITNUM | 12 },
+ { "gt.w", TIC80_OPERAND_BITNUM | 22 },
{ "gt0.b", TIC80_OPERAND_CC | 1 },
{ "gt0.h", TIC80_OPERAND_CC | 9 },
{ "gt0.w", TIC80_OPERAND_CC | 17 },
- { "hi.b", TIC80_OPERAND_BITNUM | (~6 & 0x1F) },
- { "hi.h", TIC80_OPERAND_BITNUM | (~16 & 0x1F) },
- { "hi.w", TIC80_OPERAND_BITNUM | (~26 & 0x1F) },
- { "hs.b", TIC80_OPERAND_BITNUM | (~9 & 0x1F) },
- { "hs.h", TIC80_OPERAND_BITNUM | (~19 & 0x1F) },
- { "hs.w", TIC80_OPERAND_BITNUM | (~29 & 0x1F) },
- { "ib.f", TIC80_OPERAND_BITNUM | (~28 & 0x1F) },
+ { "hi.b", TIC80_OPERAND_BITNUM | 6 },
+ { "hi.h", TIC80_OPERAND_BITNUM | 16 },
+ { "hi.w", TIC80_OPERAND_BITNUM | 26 },
+ { "hs.b", TIC80_OPERAND_BITNUM | 9 },
+ { "hs.h", TIC80_OPERAND_BITNUM | 19 },
+ { "hs.w", TIC80_OPERAND_BITNUM | 29 },
+ { "ib.f", TIC80_OPERAND_BITNUM | 28 },
{ "IE", TIC80_OPERAND_CR | 6 },
{ "ILRU", TIC80_OPERAND_CR | 0x300 },
- { "in.f", TIC80_OPERAND_BITNUM | (~27 & 0x1F) },
+ { "in.f", TIC80_OPERAND_BITNUM | 27 },
{ "IN0P", TIC80_OPERAND_CR | 0x4000 },
{ "IN1P", TIC80_OPERAND_CR | 0x4001 },
{ "INTPEN", TIC80_OPERAND_CR | 4 },
{ "ITAG7", TIC80_OPERAND_CR | 0x207 },
{ "ITAG8", TIC80_OPERAND_CR | 0x208 },
{ "ITAG9", TIC80_OPERAND_CR | 0x209 },
- { "le.b", TIC80_OPERAND_BITNUM | (~3 & 0x1F) },
- { "le.f", TIC80_OPERAND_BITNUM | (~23 & 0x1F) },
- { "le.h", TIC80_OPERAND_BITNUM | (~13 & 0x1F) },
- { "le.w", TIC80_OPERAND_BITNUM | (~23 & 0x1F) },
+ { "le.b", TIC80_OPERAND_BITNUM | 3 },
+ { "le.f", TIC80_OPERAND_BITNUM | 23 },
+ { "le.h", TIC80_OPERAND_BITNUM | 13 },
+ { "le.w", TIC80_OPERAND_BITNUM | 23 },
{ "le0.b", TIC80_OPERAND_CC | 6 },
{ "le0.h", TIC80_OPERAND_CC | 14 },
{ "le0.w", TIC80_OPERAND_CC | 22 },
- { "lo.b", TIC80_OPERAND_BITNUM | (~8 & 0x1F) },
- { "lo.h", TIC80_OPERAND_BITNUM | (~18 & 0x1F) },
- { "lo.w", TIC80_OPERAND_BITNUM | (~28 & 0x1F) },
- { "ls.b", TIC80_OPERAND_BITNUM | (~7 & 0x1F) },
- { "ls.h", TIC80_OPERAND_BITNUM | (~17 & 0x1F) },
- { "ls.w", TIC80_OPERAND_BITNUM | (~27 & 0x1F) },
- { "lt.b", TIC80_OPERAND_BITNUM | (~4 & 0x1F) },
- { "lt.f", TIC80_OPERAND_BITNUM | (~24 & 0x1F) },
- { "lt.h", TIC80_OPERAND_BITNUM | (~14 & 0x1F) },
- { "lt.w", TIC80_OPERAND_BITNUM | (~24 & 0x1F) },
+ { "lo.b", TIC80_OPERAND_BITNUM | 8 },
+ { "lo.h", TIC80_OPERAND_BITNUM | 18 },
+ { "lo.w", TIC80_OPERAND_BITNUM | 28 },
+ { "ls.b", TIC80_OPERAND_BITNUM | 7 },
+ { "ls.h", TIC80_OPERAND_BITNUM | 17 },
+ { "ls.w", TIC80_OPERAND_BITNUM | 27 },
+ { "lt.b", TIC80_OPERAND_BITNUM | 4 },
+ { "lt.f", TIC80_OPERAND_BITNUM | 24 },
+ { "lt.h", TIC80_OPERAND_BITNUM | 14 },
+ { "lt.w", TIC80_OPERAND_BITNUM | 24 },
{ "lt0.b", TIC80_OPERAND_CC | 4 },
{ "lt0.h", TIC80_OPERAND_CC | 12 },
{ "lt0.w", TIC80_OPERAND_CC | 20 },
{ "MIP", TIC80_OPERAND_CR | 0x31 },
{ "MPC", TIC80_OPERAND_CR | 0x30 },
- { "ne.b", TIC80_OPERAND_BITNUM | (~1 & 0x1F) },
- { "ne.f", TIC80_OPERAND_BITNUM | (~21 & 0x1F) },
- { "ne.h", TIC80_OPERAND_BITNUM | (~11 & 0x1F) },
- { "ne.w", TIC80_OPERAND_BITNUM | (~21 & 0x1F) },
+ { "ne.b", TIC80_OPERAND_BITNUM | 1 },
+ { "ne.f", TIC80_OPERAND_BITNUM | 21 },
+ { "ne.h", TIC80_OPERAND_BITNUM | 11 },
+ { "ne.w", TIC80_OPERAND_BITNUM | 21 },
{ "ne0.b", TIC80_OPERAND_CC | 5 },
{ "ne0.h", TIC80_OPERAND_CC | 13 },
{ "ne0.w", TIC80_OPERAND_CC | 21 },
{ "nev.b", TIC80_OPERAND_CC | 0 },
{ "nev.h", TIC80_OPERAND_CC | 8 },
{ "nev.w", TIC80_OPERAND_CC | 16 },
- { "ob.f", TIC80_OPERAND_BITNUM | (~29 & 0x1F) },
- { "or.f", TIC80_OPERAND_BITNUM | (~31 & 0x1F) },
- { "ou.f", TIC80_OPERAND_BITNUM | (~26 & 0x1F) },
+ { "ob.f", TIC80_OPERAND_BITNUM | 29 },
+ { "or.f", TIC80_OPERAND_BITNUM | 31 },
+ { "ou.f", TIC80_OPERAND_BITNUM | 26 },
{ "OUTP", TIC80_OPERAND_CR | 0x4002 },
{ "PKTREQ", TIC80_OPERAND_CR | 0xD },
{ "PPERROR", TIC80_OPERAND_CR | 0xA },
{ "r22", TIC80_OPERAND_GPR | 22 },
{ "r23", TIC80_OPERAND_GPR | 23 },
{ "r24", TIC80_OPERAND_GPR | 24 },
- { "r24", TIC80_OPERAND_GPR | 24 },
+ { "r25", TIC80_OPERAND_GPR | 25 },
{ "r26", TIC80_OPERAND_GPR | 26 },
{ "r27", TIC80_OPERAND_GPR | 27 },
{ "r28", TIC80_OPERAND_GPR | 28 },
{ "SYSTMP", TIC80_OPERAND_CR | 0x21 },
{ "TCOUNT", TIC80_OPERAND_CR | 0xE },
{ "TSCALE", TIC80_OPERAND_CR | 0xF },
- { "uo.f", TIC80_OPERAND_BITNUM | (~30 & 0x1F) },
+ { "uo.f", TIC80_OPERAND_BITNUM | 30 },
};
const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
/* Long signed PC word offset in following 32 bit word */
#define OFF_SL_PC (OFF_SS_PC + 1)
- {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
+ { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
/* Short signed base relative byte offset in bits 14-0 */
/* Long signed base relative byte offset in following 32 bit word */
#define OFF_SL_BR (OFF_SS_BR + 1)
- {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
+ { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
+
+ /* Long signed base relative byte offset in following 32 bit word
+ with optional ":s" modifier flag in bit 11 */
+
+#define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
+ { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
/* BITNUM in bits 31-27 */
-#define BITNUM (OFF_SL_BR + 1)
+#define BITNUM (OFF_SL_BR_SCALED + 1)
{ 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
/* Condition code in bits 31-27 */
#define REG_SCALED (REG_BASE_M_LI + 1)
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
- /* Long signed immediate in following 32 bit word, with optional ":s" modifier
- flag in bit 11 */
-
-#define LSI_SCALED (REG_SCALED + 1)
- { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
-
/* Unsigned immediate in bits 4-0, used only for shift instructions */
-#define ROTATE (LSI_SCALED + 1)
+#define ROTATE (REG_SCALED + 1)
{ 5, 0, NULL, NULL, 0 },
/* Unsigned immediate in bits 9-5, used only for shift instructions */
entries with the same mnemonic are sorted so that they are adjacent in the table,
allowing the use of a hash table to locate the first of a sequence of opcodes that have
a particular name. The short immediate forms also come before the long immediate forms
- so that the assembler will pick the "best fit" for the size of the operand. */
+ so that the assembler will pick the "best fit" for the size of the operand, except for
+ the case of the PC relative forms, where the long forms come first and are the default
+ forms. */
const struct tic80_opcode tic80_opcodes[] = {
/* Direct load signed data into register */
- {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
/* Direct load unsigned data into register */
- {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
/* Direct store data into memory */
- {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
/* Emulation stop */
/* Load Signed Data Into Register */
- {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} },
- {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} },
- {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST_E} },
- {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} },
- {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
+ {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
/* Load Unsigned Data Into Register */
- {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} },
- {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} },
- {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
/* Leftmost one */
/* Store Data into Memory */
- {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}},
- {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}},
- {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST_E}},
- {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
- {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}},
- {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
- {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
+ {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
+ {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
+ {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
+ {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
/* Signed Integer Subtract */