* v850-opc.c (v850_opcodes): Add null opcode to mark the

[deliverable/binutils-gdb.git] / opcodes / v850-opc.c

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 2bb8c07d0a3f501e38da91102ac309a6045e67fd..cb5c87f7b06e0bea3a472eec1564e3a688f54257 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -42,7 +42,7 @@ const struct v850_operand v850_operands[] = {
 
 /* The IMM16 field in a format 6 insn. */
 #define I16    (I5U+1)
-  { 16, 16, 0, 0, 0 }, 
+  { 16, 16, 0, 0, V850_OPERAND_SIGNED }, 
 
 /* The signed DISP7 field in a format 4 insn. */
 #define D7S    (I16+1)
@@ -74,10 +74,15 @@ const struct v850_operand v850_operands[] = {
 
 /* System register operands.  */
 #define SR1    (D8+1)
-  { 5, 0, 0, 0, V850_OPERAND_SRG }, 
+  { 5, 0, 0, 0, V850_OPERAND_SRG },
+
+/* EP Register.  */
+#define EP     (SR1+1)
+  { 0, 0, 0, 0, V850_OPERAND_EP },
 
-#define SR2    (SR1+1)
-  { 5, 11, 0, 0, V850_OPERAND_SRG },
+/* The IMM16 field (unsigned0 in a format 6 insn. */
+#define I16U   (EP+1)
+  { 16, 16, 0, 0, 0}, 
 } ; 
 
 \f
@@ -91,10 +96,10 @@ const struct v850_operand v850_operands[] = {
 #define IF3    {D9}
 
 /* 16-bit load/store instruction (Format IV) */
-#define IF4A   {D7S, R1, R2}
-#define IF4B   {R2, D7S, R1}
-#define IF4C   {D8, R1, R2}
-#define IF4D   {R2, D8, R1}
+#define IF4A   {D7S, EP, R2}
+#define IF4B   {R2, D7S, EP}
+#define IF4C   {D8, EP, R2}
+#define IF4D   {R2, D8, EP}
 
 /* Jump instruction (Format V) */
 #define IF5    {D22}
@@ -102,6 +107,9 @@ const struct v850_operand v850_operands[] = {
 /* 3 operand instruction (Format VI) */
 #define IF6    {I16, R1, R2}
 
+/* 3 operand instruction (Format VI) */
+#define IF6U   {I16U, R1, R2}
+
 /* 32-bit load/store instruction (Format VII) */
 #define IF7A   {D16, R1, R2}
 #define IF7B   {R2, D16, R1}
@@ -129,25 +137,25 @@ const struct v850_operand v850_operands[] = {
 
 const struct v850_opcode v850_opcodes[] = {
 /* load/store instructions */
-{ "sld.b",     OP(0x00),               OP_MASK,        IF4A, 2 },
-{ "sld.h",     OP(0x00),               OP_MASK,        IF4C, 2 },
-{ "sld.w",     OP(0x00),               OP_MASK,        IF4C, 2 },
+{ "sld.b",     one(0x0300),            one(0x0780),    IF4A, 2 },
+{ "sld.h",     one(0x0400),            one(0x0780),    IF4A, 2 },
+{ "sld.w",     one(0x0500),            one(0x0780),    IF4A, 2 },
 { "sst.b",     OP(0x00),               OP_MASK,        IF4B, 2 },
 { "sst.h",     OP(0x00),               OP_MASK,        IF4D, 2 },
 { "sst.w",     OP(0x00),               OP_MASK,        IF4D, 2 },
 
-{ "ld.b",      OP(0x00),               OP_MASK,        IF7A, 4 },
-{ "ld.h",      OP(0x00),               OP_MASK,        IF7A, 4 },
-{ "ld.w",      OP(0x00),               OP_MASK,        IF7A, 4 },
-{ "st.b",      OP(0x00),               OP_MASK,        IF7B, 4 },
-{ "st.h",      OP(0x00),               OP_MASK,        IF7B, 4 },
-{ "st.w",      OP(0x00),               OP_MASK,        IF7B, 4 },
+{ "ld.b",      two(0x0700,0x0000),     two (0x07e0,0x0000),    IF7A, 4 },
+{ "ld.h",      two(0x0720,0x0000),     two (0x07e0,0x0001),    IF7A, 4 },
+{ "ld.w",      two(0x0720,0x0001),     two (0x07e0,0x0001),    IF7A, 4 },
+{ "st.b",      two(0x0740,0x0000),     two (0x07e0,0x0000),    IF7B, 4 },
+{ "st.h",      two(0x0760,0x0000),     two (0x07e0,0x0001),    IF7B, 4 },
+{ "st.w",      two(0x0760,0x0001),     two (0x07e0,0x0001),    IF7B, 4 },
 
 /* arithmetic operation instructions */
 { "mov",        OP(0x00),              OP_MASK,        IF1, 2 },
-{ "mov",       OP(0x08),               OP_MASK,        IF2, 2 },
+{ "mov",       OP(0x10),               OP_MASK,        IF2, 2 },
 { "movea",     OP(0x31),               OP_MASK,        IF6, 4 },
-{ "movhi",     OP(0x31),               OP_MASK,        IF6, 4 },
+{ "movhi",     OP(0x32),               OP_MASK,        IF6, 4 },
 { "add",       OP(0x0e),               OP_MASK,        IF1, 2 },
 { "add",       OP(0x12),               OP_MASK,        IF2, 2 },
 { "addi",      OP(0x30),               OP_MASK,        IF6, 4 },
@@ -171,11 +179,11 @@ const struct v850_opcode v850_opcodes[] = {
 /* logical operation instructions */
 { "tst",       OP(0x0b),               OP_MASK,        IF1, 2 },
 { "or",                OP(0x08),               OP_MASK,        IF1, 2 },
-{ "ori",       OP(0x34),               OP_MASK,        IF6, 4 },
+{ "ori",       OP(0x34),               OP_MASK,        IF6U, 4 },
 { "and",       OP(0x0a),               OP_MASK,        IF1, 2 },
-{ "andi",      OP(0x36),               OP_MASK,        IF6, 4 },
+{ "andi",      OP(0x36),               OP_MASK,        IF6U, 4 },
 { "xor",       OP(0x09),               OP_MASK,        IF1, 2 },
-{ "xori",      OP(0x35),               OP_MASK,        IF6, 4 },
+{ "xori",      OP(0x35),               OP_MASK,        IF6U, 4 },
 { "not",       OP(0x01),               OP_MASK,        IF1, 2 },
 { "sar",       OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 { "sar",       two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
@@ -226,9 +234,10 @@ const struct v850_opcode v850_opcodes[] = {
 { "halt",      two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 4 },
 { "reti",      two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 4 },
 { "trap",      two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 4 },
-{ "ldsr",      two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R1,SR2}, 4 },
+{ "ldsr",      two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R2,SR1}, 4 },
 { "stsr",      two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 4 },
 { "nop",       one(0x00),              one(0xff),              {0}, 2 },
+{ 0, 0, 0, {0}, 0 },
 
 } ;