#include "ansidecl.h"
#include "opcode/v850.h"
+/* Local insertion and extraction functions. */
+static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
+static long extract_d9 PARAMS ((unsigned long, int *));
+
/* regular opcode */
#define OP(x) ((x & 0x3f) << 5)
#define OP_MASK OP(0x3f)
\f
const struct v850_operand v850_operands[] = {
#define UNUSED 0
- { 0, 0, 0 },
+ { 0, 0, 0, 0, 0 },
/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1 (UNUSED+1)
- { 5, 0, OPERAND_REG },
+ { 5, 0, 0, 0, V850_OPERAND_REG },
/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2 (R1+1)
- { 5, 11, OPERAND_REG },
+ { 5, 11, 0, 0, V850_OPERAND_REG },
/* The IMM5 field in a format 2 insn. */
#define I5 (R2+1)
- { 5, 0, OPERAND_NUM },
+ { 5, 0, 0, 0, V850_OPERAND_SIGNED },
+
+#define I5U (I5+1)
+ { 5, 0, 0, 0, 0 },
-#define IMM16 field in a format 6 insn. */
-#define I16 (I5+1)
- { 16, 0, OPERAND_NUM },
+/* The IMM16 field in a format 6 insn. */
+#define I16 (I5U+1)
+ { 16, 0, 0, 0, 0 },
/* The DISP6 field in a format 4 insn. */
#define D6 (I16+1)
- { 6, 1, OPERAND_NUM },
+ { 6, 1, 0, 0, 0 },
-/* The DISP8 field in a format 3 insn. */
-#define D8 (D6+1)
- { 9, 0, OPERAND_NUM },
+/* The DISP9 field in a format 3 insn. */
+#define D9 (D6+1)
+ { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
/* The DISP16 field in a format 6 insn. */
-#define D16 (D8+1)
- { 16, 0, OPERAND_NUM },
+#define D16 (D9+1)
+ { 16, 0, 0, 0, V850_OPERAND_SIGNED },
/* The DISP22 field in a format 4 insn. */
#define D22 (D16+1)
- { 16, 0, OPERAND_NUM },
+ { 16, 0, 0, 0, 0 },
#define B3 (D22+1)
/* The 3 bit immediate field in format 8 insn. */
- { 3, 3, OPERAND_NUM }
+ { 3, 11, 0, 0, 0 },
+
+#define CCCC (B3+1)
+/* The 4 bit condition code in a setf instruction */
+ { 4, 0, 0, 0, V850_OPERAND_CC }
} ;
\f
#define IF2 {I5, R2}
/* conditional branch instruction format (Format III) */
-#define IF3 {D8}
+#define IF3 {D9}
/* 16-bit load/store instruction (Format IV) */
-#define IF4 {D6}
+#define IF4A {D6, R2}
+#define IF4B {R2, D6}
/* Jump instruction (Format V) */
#define IF5 {D22}
/* 3 operand instruction (Format VI) */
-#define IF6 {R1, R2, I16}
+#define IF6 {I16, R1, R2}
/* 32-bit load/store instruction (Format VII) */
-#define IF7 {R1, R2, D16}
+#define IF7A {D16, R1, R2}
+#define IF7B {R2, D16, R1}
/* Bit manipulation function. */
const struct v850_opcode v850_opcodes[] = {
/* load/store instructions */
-/* XXX */
+{ "sld.b", OP(0x00), OP_MASK, IF4A },
+{ "sld.h", OP(0x00), OP_MASK, IF4A },
+{ "sld.w", OP(0x00), OP_MASK, IF4A },
+{ "sst.b", OP(0x00), OP_MASK, IF4B },
+{ "sst.h", OP(0x00), OP_MASK, IF4B },
+{ "sst.w", OP(0x00), OP_MASK, IF4B },
+
+{ "ld.b", OP(0x00), OP_MASK, IF7A },
+{ "ld.h", OP(0x00), OP_MASK, IF7A },
+{ "ld.w", OP(0x00), OP_MASK, IF7A },
+{ "st.b", OP(0x00), OP_MASK, IF7B },
+{ "st.h", OP(0x00), OP_MASK, IF7B },
+{ "st.w", OP(0x00), OP_MASK, IF7B },
/* arithmetic operation instructions */
{ "mov", OP(0x00), OP_MASK, IF1 },
{ "divh", OP(0x02), OP_MASK, IF1 },
{ "cmp", OP(0x0f), OP_MASK, IF1 },
{ "cmp", OP(0x13), OP_MASK, IF2 },
-/* XXX missing setf */
+{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} },
/* saturated operation instructions */
{ "satadd", OP(0x06), OP_MASK, IF1 },
{ "xor", OP(0x09), OP_MASK, IF1 },
{ "xori", OP(0x35), OP_MASK, IF6 },
{ "not", OP(0x01), OP_MASK, IF1 },
-{ "sar", OP(0x15), OP_MASK, IF2 },
+{ "sar", OP(0x15), OP_MASK, {I5U, R2} },
{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
-{ "shl", OP(0x16), OP_MASK, IF2 },
+{ "shl", OP(0x16), OP_MASK, {I5U, R2} },
{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
-{ "shr", OP(0x14), OP_MASK, IF2 },
+{ "shr", OP(0x14), OP_MASK, {I5U, R2} },
{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
/* branch instructions */
{ "bsa", BOP(0xd), BOP_MASK, IF3 },
{ "jmp", one(0x0060), one(0xffe0), R1 },
-{ "jarl", one(0x0780), one(0xf83f), { R2,D22 } },
+{ "jarl", one(0x0780), one(0xf83f), { D22, R2 } },
{ "jr", one(0x0780), one(0xffe0), { D22 } },
/* bit manipulation instructions */
-{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} },
-{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} },
-{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} },
-{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} },
+{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
+{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
+{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
+{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
/* special instructions */
{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
-#if 0
{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} },
-#endif
{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} },
{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} },
{ "nop", one(0x00), one(0xff), {0} },
const int v850_num_opcodes =
sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
+\f
+/* The functions used to insert and extract complicated operands. */
+
+static unsigned long
+insert_d9 (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg;
+{
+ if (value > 511 || value <= -512)
+ *errmsg = "value out of range";
+
+ return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
+}
+
+static long
+extract_d9 (insn, invalid)
+ unsigned long insn;
+ int *invalid;
+{
+ long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
+
+ if ((insn & 0x8000) != 0)
+ ret -= 0x0200;
+
+ return ret;
+}
projects / deliverable / binutils-gdb.git / blobdiff