Don't write to inferior_ptid in target.c

[deliverable/binutils-gdb.git] / sim / aarch64 / ChangeLog

diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog
index 0b3d21dec840b228ede88438ff4461dbe7f3769c..1b907b94c9c506d50540aca4a2234089ca5db82d 100644 (file)
--- a/sim/aarch64/ChangeLog
+++ b/sim/aarch64/ChangeLog
@@ -1,5 +1,34 @@
+2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
+
+       PR sim/25318
+       * simulator.c (blr): Read destination register before calling
+       aarch64_save_LR.
+
+2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * cpustate.c: Add 'libiberty.h' include.
+       * interp.c: Add 'sim-assert.h' include.
+
+2017-09-06  John Baldwin  <jhb@FreeBSD.org>
+
+       * configure: Regenerate.
+
+2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
+
+       * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
+       registers based on structure size.
+       (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
+       (LD1_1): Replace with call to vec_load.
+       (vec_store): Add new M argument.  Rewrite to iterate over registers
+       based on structure size.
+       (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
+       (ST1_1): Replace with call to vec_store.
+
 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 
+       * simulator.c (do_vec_FCVTL): New.
+       (do_vec_op1): Call do_vec_FCVTL.
+
        * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
        do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
        (do_scalar_vec): Add calls to new functions.