sim: drop redundant SIM_AC_OPTION_WARNINGS

[deliverable/binutils-gdb.git] / sim / aarch64 / cpustate.h

diff --git a/sim/aarch64/cpustate.h b/sim/aarch64/cpustate.h
index 49379d6a028bee2bc182c956aa968d3700df6f0e..b9e1f92d640ab36e2f388097a5f9b7c592ec79cb 100644 (file)
--- a/sim/aarch64/cpustate.h
+++ b/sim/aarch64/cpustate.h
@@ -1,6 +1,6 @@
 /* cpustate.h -- Prototypes for AArch64 cpu state functions.
 
-   Copyright (C) 2015-2016 Free Software Foundation, Inc.
+   Copyright (C) 2015-2021 Free Software Foundation, Inc.
 
    Contributed by Red Hat.
 
@@ -26,7 +26,7 @@
 #include <stdint.h>
 #include <inttypes.h>
 
-#include "gdb/remote-sim.h"
+#include "sim/sim.h"
 
 /* Symbolic names used to identify general registers which also match
    the registers indices in machine code.
@@ -123,16 +123,14 @@ typedef enum VReg
 } VReg;
 
 /* All the different integer bit patterns for the components of a
-   general register are overlaid here using a union so as to allow all
-   reading and writing of the desired bits.
-
-   N.B. the ARM spec says that when you write a 32 bit register you
-   are supposed to write the low 32 bits and zero the high 32
-   bits. But we don't actually have to care about this because Java
-   will only ever consume the 32 bits value as a 64 bit quantity after
-   an explicit extend.  */
+   general register are overlaid here using a union so as to allow
+   all reading and writing of the desired bits.  Note that we have
+   to take care when emulating a big-endian AArch64 as we are
+   running on a little endian host.  */
+
 typedef union GRegisterValue
 {
+#if !WORDS_BIGENDIAN
   int8_t   s8;
   int16_t  s16;
   int32_t  s32;
@@ -141,6 +139,16 @@ typedef union GRegisterValue
   uint16_t u16;
   uint32_t u32;
   uint64_t u64;
+#else
+  struct { int64_t :56; int8_t s8; };
+  struct { int64_t :48; int16_t s16; };
+  struct { int64_t :32; int32_t s32; };
+  int64_t s64;
+  struct { uint64_t :56; uint8_t u8; };
+  struct { uint64_t :48; uint16_t u16; };
+  struct { uint64_t :32; uint32_t u32; };
+  uint64_t u64;
+#endif
 } GRegister;
 
 /* Float registers provide for storage of a single, double or quad
@@ -269,7 +277,9 @@ extern uint32_t    aarch64_get_reg_u8  (sim_cpu *, GReg, int);
 extern int32_t     aarch64_get_reg_s8  (sim_cpu *, GReg, int);
 
 extern void        aarch64_set_reg_u64 (sim_cpu *, GReg, int, uint64_t);
+extern void        aarch64_set_reg_u32 (sim_cpu *, GReg, int, uint32_t);
 extern void        aarch64_set_reg_s64 (sim_cpu *, GReg, int, int64_t);
+extern void        aarch64_set_reg_s32 (sim_cpu *, GReg, int, int32_t);
 
 /* FP Register access functions.  */
 extern float       aarch64_get_FP_half   (sim_cpu *, VReg);