[ARM, sim] Fix build error and warnings

[deliverable/binutils-gdb.git] / sim / arm / armemu.h

diff --git a/sim/arm/armemu.h b/sim/arm/armemu.h
index 63e6ecd12a6f79ccfca6f496b7c7ba54405d32ba..7f25b94d51cb70ea6cf0b0480737aed49aaf0955 100644 (file)
--- a/sim/arm/armemu.h
+++ b/sim/arm/armemu.h
@@ -12,10 +12,13 @@
     GNU General Public License for more details.
  
     You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+    along with this program; if not, see <http://www.gnu.org/licenses/>. */
 
 extern ARMword isize;
+extern int trace;
+extern int disas;
+extern int trace_funcs;
+extern void print_insn (ARMword);
 
 /* Condition code values.  */
 #define EQ 0
@@ -47,6 +50,10 @@ extern ARMword isize;
 #define CBIT (1L << 29)
 #define VBIT (1L << 28)
 #define SBIT (1L << 27)
+#define GE0 (1L << 16)
+#define GE1 (1L << 17)
+#define GE2 (1L << 18)
+#define GE3 (1L << 19)
 #define IBIT (1L << 7)
 #define FBIT (1L << 6)
 #define IFBITS (3L << 6)
@@ -403,7 +410,7 @@ extern ARMword isize;
   do                                           \
     {                                          \
       if (DESTReg == 15)                       \
-       WriteR15Branch (state, d);              \
+       WriteR15Load (state, d);                \
       else                                     \
        DEST = d;                               \
     }                                          \
@@ -455,31 +462,34 @@ typedef enum
 }
 tdstate;
 
-/* Macros to scrutinize instructions.  */
-#define UNDEF_Test
-#define UNDEF_Shift
-#define UNDEF_MSRPC
-#define UNDEF_MRSPC
-#define UNDEF_MULPCDest
-#define UNDEF_MULDestEQOp1
-#define UNDEF_LSRBPC
-#define UNDEF_LSRBaseEQOffWb
-#define UNDEF_LSRBaseEQDestWb
-#define UNDEF_LSRPCBaseWb
-#define UNDEF_LSRPCOffWb
-#define UNDEF_LSMNoRegs
-#define UNDEF_LSMPCBase
-#define UNDEF_LSMUserBankWb
-#define UNDEF_LSMBaseInListWb
-#define UNDEF_SWPPC
-#define UNDEF_CoProHS
-#define UNDEF_MCRPC
-#define UNDEF_LSCPCBaseWb
-#define UNDEF_UndefNotBounced
-#define UNDEF_ShortInt
-#define UNDEF_IllegalMode
-#define UNDEF_Prog32SigChange
-#define UNDEF_Data32SigChange
+#define t_resolved t_branch
+
+/* Macros to scrutinize instructions.  The dummy do loop is to keep the compiler
+   happy when the statement is used in an otherwise empty else statement.  */
+#define UNDEF_Test             do { ; } while (0)
+#define UNDEF_Shift            do { ; } while (0)
+#define UNDEF_MSRPC            do { ; } while (0)
+#define UNDEF_MRSPC            do { ; } while (0)
+#define UNDEF_MULPCDest                do { ; } while (0)
+#define UNDEF_MULDestEQOp1     do { ; } while (0)
+#define UNDEF_LSRBPC           do { ; } while (0)
+#define UNDEF_LSRBaseEQOffWb   do { ; } while (0)
+#define UNDEF_LSRBaseEQDestWb  do { ; } while (0)
+#define UNDEF_LSRPCBaseWb      do { ; } while (0)
+#define UNDEF_LSRPCOffWb       do { ; } while (0)
+#define UNDEF_LSMNoRegs                do { ; } while (0)
+#define UNDEF_LSMPCBase                do { ; } while (0)
+#define UNDEF_LSMUserBankWb    do { ; } while (0)
+#define UNDEF_LSMBaseInListWb  do { ; } while (0)
+#define UNDEF_SWPPC            do { ; } while (0)
+#define UNDEF_CoProHS          do { ; } while (0)
+#define UNDEF_MCRPC            do { ; } while (0)
+#define UNDEF_LSCPCBaseWb      do { ; } while (0)
+#define UNDEF_UndefNotBounced  do { ; } while (0)
+#define UNDEF_ShortInt         do { ; } while (0)
+#define UNDEF_IllegalMode      do { ; } while (0)
+#define UNDEF_Prog32SigChange  do { ; } while (0)
+#define UNDEF_Data32SigChange  do { ; } while (0)
 
 /* Prototypes for exported functions.  */
 extern unsigned ARMul_NthReg        (ARMword, unsigned);