#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )
-#ifdef MODET /* Thumb support */
+#ifdef MODET /* Thumb support */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
It isn't clear if the simulator needs to model that or not. */
#define TBIT (1L << 5)
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
+#define INSN_SIZE (TFLAG ? 2 : 4)
+#else
+#define INSN_SIZE 4
#endif
#define NFLAG state->NFlag
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res
+
#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
+#define PSR_FBITS (0xff000000L)
+#define PSR_SBITS (0x00ff0000L)
+#define PSR_XBITS (0x0000ff00L)
+#define PSR_CBITS (0x000000ffL)
+
#define CCBITS (0xf0000000L)
#define INTBITS (0xc0L)
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif
-#define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
-#define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS)
-#define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS))
-#define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS)
+#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
+#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
+#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
+#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
+#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
} \
else { \
- state->Reg[15] = R15PC | (s) & (CCBITS | R15INTBITS | R15MODEBITS) ; \
- ARMul_R15Altered(state) ; \
+ state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
+ ARMul_R15Altered (state) ; \
}
-#define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
+#define SETABORT(i,m,d) do { \
+ int SETABORT_mode = (m); \
+ ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
+ ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
+ | (i) | SETABORT_mode)); \
+ state->Reg[14] = temp - (d); \
+} while (0)
#ifndef MODE32
#define VECTORS 0x20
#define RESUME 8
#define NORMALCYCLE state->NextInstr = 0
-#define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
-#define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
- state->NextInstr = (state->NextInstr & 0xff) | 2
-#define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
- state->NextInstr |= 3
+#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
+#define BUSUSEDINCPCS \
+ do \
+ { \
+ if (! state->is_v4) \
+ { \
+ state->Reg[15] += isize ; /* A standard PC inc and an S cycle. */ \
+ state->NextInstr = (state->NextInstr & 0xff) | 2; \
+ } \
+ } \
+ while (0)
+#define BUSUSEDINCPCN \
+ do \
+ { \
+ if (state->is_v4) \
+ BUSUSEDN; \
+ else \
+ { \
+ state->Reg[15] += isize ; /* A standard PC inc and an N cycle. */ \
+ state->NextInstr |= 3; \
+ } \
+ } \
+ while (0)
#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
state->NextInstr |= 2
#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
ARMul_NegZero(state, d) ; \
}
+#define WRITEDESTB(d) if (DESTReg == 15) \
+ WriteR15Branch(state, d) ; \
+ else \
+ DEST = d
+
#define BYTETOBUS(data) ((data & 0xff) | \
((data & 0xff) << 8) | \
((data & 0xff) << 16) | \
#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
#define POSBRANCH ((instr & 0x7fffff) << 2)
-#define NEGBRANCH (0xff000000 | ((instr & 0xffffff) << 2))
+#define NEGBRANCH (0xfc000000 | ((instr & 0xffffff) << 2))
/***************************************************************************\
* Values for Emulate *
\***************************************************************************/
-#define STOP 0 /* stop */
-#define CHANGEMODE 1 /* change mode */
-#define ONCE 2 /* execute just one interation */
-#define RUN 3 /* continuous execution */
+#define STOP 0 /* stop */
+#define CHANGEMODE 1 /* change mode */
+#define ONCE 2 /* execute just one interation */
+#define RUN 3 /* continuous execution */
/***************************************************************************\
* Stuff that is shared across modes *
\***************************************************************************/
-extern ARMword ARMul_Emulate26(ARMul_State *state) ;
-extern ARMword ARMul_Emulate32(ARMul_State *state) ;
-extern unsigned ARMul_MultTable[] ; /* Number of I cycles for a mult */
-extern ARMword ARMul_ImmedTable[] ; /* immediate DP LHS values */
-extern char ARMul_BitList[] ; /* number of bits in a byte table */
-extern void ARMul_Abort26(ARMul_State *state, ARMword) ;
-extern void ARMul_Abort32(ARMul_State *state, ARMword) ;
-extern unsigned ARMul_NthReg(ARMword instr,unsigned number) ;
-extern void ARMul_MSRCpsr(ARMul_State *state, ARMword instr, ARMword rhs) ;
-extern void ARMul_NegZero(ARMul_State *state, ARMword result) ;
-extern void ARMul_AddCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_AddOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_SubCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_SubOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_CPSRAltered(ARMul_State *state) ;
-extern void ARMul_R15Altered(ARMul_State *state) ;
-extern ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode) ;
-extern unsigned ARMul_NthReg(ARMword instr, unsigned number) ;
-extern void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address) ;
-extern void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address) ;
-extern void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source) ;
-extern ARMword ARMul_MRC(ARMul_State *state,ARMword instr) ;
-extern void ARMul_CDP(ARMul_State *state,ARMword instr) ;
-extern unsigned IntPending(ARMul_State *state) ;
-extern ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data) ;
+extern ARMword ARMul_Emulate26 (ARMul_State * state);
+extern ARMword ARMul_Emulate32 (ARMul_State * state);
+extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult */
+extern ARMword ARMul_ImmedTable[]; /* immediate DP LHS values */
+extern char ARMul_BitList[]; /* number of bits in a byte table */
+extern void ARMul_Abort26 (ARMul_State * state, ARMword);
+extern void ARMul_Abort32 (ARMul_State * state, ARMword);
+extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
+extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
+extern void ARMul_NegZero (ARMul_State * state, ARMword result);
+extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern int AddOverflow (ARMword a, ARMword b, ARMword result);
+extern int SubOverflow (ARMword a, ARMword b, ARMword result);
+extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern void ARMul_CPSRAltered (ARMul_State * state);
+extern void ARMul_R15Altered (ARMul_State * state);
+extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
+ ARMword newmode);
+extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
+extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
+extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
+extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
+extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
+extern void ARMul_CDP (ARMul_State * state, ARMword instr);
+extern unsigned IntPending (ARMul_State * state);
+extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
+ ARMword data);
#define EVENTLISTSIZE 1024L
/* Thumb support: */
-typedef enum {
- t_undefined, /* undefined Thumb instruction */
- t_decoded, /* instruction decoded to ARM equivalent */
- t_branch /* Thumb branch (already processed) */
-} tdstate;
+typedef enum
+{
+ t_undefined, /* undefined Thumb instruction */
+ t_decoded, /* instruction decoded to ARM equivalent */
+ t_branch /* Thumb branch (already processed) */
+}
+tdstate;
-extern tdstate ARMul_ThumbDecode(ARMul_State *state,ARMword pc,ARMword tinstr, ARMword *ainstr);
+extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
+ ARMword tinstr, ARMword * ainstr);
/***************************************************************************\
* Macros to scrutinize instructions *
#define UNDEF_IllegalMode
#define UNDEF_Prog32SigChange
#define UNDEF_Data32SigChange
-
projects / deliverable / binutils-gdb.git / blobdiff