sim: add helper macros for branch profiling

[deliverable/binutils-gdb.git] / sim / arm / thumbemu.c

diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index 283e7d5cf5ad1fecee5411939cdaa51389f0605d..8707ca71a64b09a498750b5717d3ba551d7d9dc1 100644 (file)
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -13,7 +13,7 @@
  
     You should have received a copy of the GNU General Public License
     along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
 
 /* We can provide simple Thumb simulation by decoding the Thumb
 instruction into its corresponding ARM instruction, and using the
@@ -31,20 +31,74 @@ existing ARM simulator.  */
 #include "armemu.h"
 #include "armos.h"
 
+/* Attempt to emulate an ARMv6 instruction.
+   Stores t_branch into PVALUE upon success or t_undefined otherwise.  */
+
+static void
+handle_v6_thumb_insn (ARMul_State * state,
+                     ARMword       tinstr,
+                     tdstate *     pvalid)
+{
+  ARMword Rd;
+  ARMword Rm;
+
+  if (! state->is_v6)
+    {
+      * pvalid = t_undefined;
+      return;
+    }
+
+  switch (tinstr & 0xFFC0)
+    {
+    case 0xb660: /* cpsie */
+    case 0xb670: /* cpsid */
+    case 0x4600: /* cpy */
+    case 0xba00: /* rev */
+    case 0xba40: /* rev16 */
+    case 0xbac0: /* revsh */
+    case 0xb650: /* setend */
+    default:  
+      printf ("Unhandled v6 thumb insn: %04x\n", tinstr);
+      * pvalid = t_undefined;
+      return;
+
+    case 0xb200: /* sxth */
+      Rm = state->Reg [(tinstr & 0x38) >> 3];
+      if (Rm & 0x8000)
+       state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000;
+      else
+       state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
+      break;
+    case 0xb240: /* sxtb */
+      Rm = state->Reg [(tinstr & 0x38) >> 3];
+      if (Rm & 0x80)
+       state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00;
+      else
+       state->Reg [(tinstr & 0x7)] = Rm & 0xff;
+      break;
+    case 0xb280: /* uxth */
+      Rm = state->Reg [(tinstr & 0x38) >> 3];
+      state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
+      break;
+    case 0xb2c0: /* uxtb */
+      Rm = state->Reg [(tinstr & 0x38) >> 3];
+      state->Reg [(tinstr & 0x7)] = Rm & 0xff;
+      break;
+    }
+  /* Indicate that the instruction has been processed.  */
+  * pvalid = t_branch;
+}
+
 /* Decode a 16bit Thumb instruction.  The instruction is in the low
    16-bits of the tinstr field, with the following Thumb instruction
    held in the high 16-bits.  Passing in two Thumb instructions allows
    easier simulation of the special dual BL instruction.  */
 
-tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
-     ARMul_State *
-       state;
-     ARMword
-       pc;
-     ARMword
-       tinstr;
-     ARMword *
-       ainstr;
+tdstate
+ARMul_ThumbDecode (ARMul_State * state,
+                  ARMword       pc,
+                  ARMword       tinstr,
+                  ARMword *     ainstr)
 {
   tdstate valid = t_decoded;   /* default assumes a valid instruction */
   ARMword next_instr;
@@ -222,7 +276,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
            case 0x0:           /* UNDEFINED */
            case 0x4:           /* UNDEFINED */
            case 0x8:           /* UNDEFINED */
-             valid = t_undefined;
+             handle_v6_thumb_insn (state, tinstr, & valid);
              break;
            }
        }
@@ -370,7 +424,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
          /* Drop through.  */
        default:
          /* Everything else is an undefined instruction.  */
-         valid = t_undefined;
+         handle_v6_thumb_insn (state, tinstr, & valid);
          break;
        }
       break;
@@ -460,8 +514,9 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
            }
          valid = t_branch;
        }
-      else                     /* UNDEFINED : cc=1110(AL) uses different format */
-       valid = t_undefined;
+      else
+       /* UNDEFINED : cc=1110(AL) uses different format.  */
+       handle_v6_thumb_insn (state, tinstr, & valid);
       break;
     case 28:                   /* B */
       /* Format 18 */
@@ -476,7 +531,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
        {
          if (tinstr & 1)
            {
-             valid = t_undefined;
+             handle_v6_thumb_insn (state, tinstr, & valid);
              break;
            }
          /* Drop through.  */
@@ -489,7 +544,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
             if r14 is not suitably initialised.  */
          {
            ARMword tmp = (pc + 2);
-           
+
            state->Reg[15] = ((state->Reg[14] + ((tinstr & 0x07FF) << 1))
                              & 0xFFFFFFFC);
            CLEART;
@@ -499,8 +554,10 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
            break;
          }
        }
-      valid = t_undefined;
+
+      handle_v6_thumb_insn (state, tinstr, & valid);
       break;
+
     case 30:                   /* BL instruction 1 */
       /* Format 19 */
       /* There is no single ARM instruction equivalent for this Thumb
@@ -509,8 +566,9 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
          second half of this BL, and if it is we simulate it
          immediately.  */
       state->Reg[14] = state->Reg[15] \
-       +(((tinstr & 0x07FF) << 12) \
-         |((tinstr & (1 << 10)) ? 0xFF800000 : 0));
+       + (((tinstr & 0x07FF) << 12) \
+          | ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
+
       valid = t_branch;                /* in-case we don't have the 2nd half */
       tinstr = next_instr;     /* move the instruction down */
       pc += 2;                 /* point the pc at the 2nd half */
@@ -543,7 +601,8 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
          the simulation of it on its own, with undefined results if
          r14 is not suitably initialised.  */
       {
-       ARMword tmp = (pc + 2);
+       ARMword tmp = pc;
+
        state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1));
        state->Reg[14] = (tmp | 1);
        valid = t_branch;