/* Blackfin Direct Memory Access (DMA) Channel model.
- Copyright (C) 2010-2011 Free Software Foundation, Inc.
+ Copyright (C) 2010-2020 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
/* XXX: This sucks performance wise. */
nr_bytes = dma->ele_size;
else
- nr_bytes = MIN (sizeof (buf), dma->curr_x_count * dma->ele_size);
+ nr_bytes = min (sizeof (buf), dma->curr_x_count * dma->ele_size);
/* Pumping a chunk! */
bfin_peer->dma_master = me;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
if (nr_bytes == 4)
*value32p = value;
else
- *value16p = value;
+ *value16p = value;
}
else
HW_TRACE ((me, "discarding write while dma running"));
default:
/* XXX: The HW lets the pad regions be read/written ... */
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr % dma->base;
valuep = (void *)((unsigned long)dma + mmr_base() + mmr_off);
value16p = valuep;