Add missing changelog entries of last commit

[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_pll.c

diff --git a/sim/bfin/dv-bfin_pll.c b/sim/bfin/dv-bfin_pll.c
index b6e110a7ee5abf7912d1f9f9f6181389544c78c6..7729180f73a199867a359aee78e51a33ec332361 100644 (file)
--- a/sim/bfin/dv-bfin_pll.c
+++ b/sim/bfin/dv-bfin_pll.c
@@ -1,6 +1,6 @@
 /* Blackfin Phase Lock Loop (PLL) model.
 
-   Copyright (C) 2010-2011 Free Software Foundation, Inc.
+   Copyright (C) 2010-2015 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
@@ -42,7 +42,8 @@ struct bfin_pll
 #define mmr_base()      offsetof(struct bfin_pll, pll_ctl)
 #define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base())
 
-static const char * const mmr_names[] = {
+static const char * const mmr_names[] =
+{
   "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID",
 };
 #define mmr_name(off) mmr_names[(off) / 4]
@@ -117,7 +118,8 @@ bfin_pll_io_read_buffer (struct hw *me, void *dest,
   return nr_bytes;
 }
 
-static const struct hw_port_descriptor bfin_pll_ports[] = {
+static const struct hw_port_descriptor bfin_pll_ports[] =
+{
   { "pll", 0, 0, output_port, },
   { NULL, 0, 0, 0, },
 };
@@ -181,7 +183,8 @@ bfin_pll_finish (struct hw *me)
   pll->pll_lockcnt = 0x300;
 }
 
-const struct hw_descriptor dv_bfin_pll_descriptor[] = {
+const struct hw_descriptor dv_bfin_pll_descriptor[] =
+{
   {"bfin_pll", bfin_pll_finish,},
   {NULL, NULL},
 };