/* Blackfin Phase Lock Loop (PLL) model.
- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+ Copyright (C) 2010-2017 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
switch (mmr_off)
{
case mmr_offset(pll_stat):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
case mmr_offset(chipid):
/* Discard writes. */
break;
default:
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
break;
}
bu16 *value16p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - pll->base;
valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
value16p = valuep;
dv_store_4 (dest, *value32p);
break;
default:
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
}