/* Simulator for Analog Devices Blackfin processors.
- Copyright (C) 2005-2011 Free Software Foundation, Inc.
- Contributed by Analog Devices, Inc.
+ Copyright (C) 2005-2014 Free Software Foundation, Inc.
+ Contributed by Analog Devices, Inc. and Mike Frysinger.
This file is part of simulators.
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
+ DEVICE (0, 0, "glue-or@1"),
+ DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
+ DEVICE (0, 0, "glue-or@2"),
+ DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
+ DEVICE (0, 0, "glue-or@17"),
+ DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
+ DEVICE (0, 0, "glue-or@18"),
+ DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
+ DEVICE (0, 0, "glue-or@27"),
+ DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
+ DEVICE (0, 0, "glue-or@31"),
+ DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
};
static const struct bfin_dev_layout bf537_dev[] =
{
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
+ DEVICE (0, 0, "glue-or@1"),
+ DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
+ DEVICE (0, 0, "glue-or@2"),
+ DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
+ DEVICE (0, 0, "glue-or@17"),
+ DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
+ DEVICE (0, 0, "glue-or@18"),
+ DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
+ DEVICE (0, 0, "glue-or@27"),
+ DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
+ DEVICE (0, 0, "glue-or@31"),
+ DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
};
#define bf536_dev bf537_dev
#define bf534_dmac bf50x_dmac
static const struct bfin_port_layout bf537_port[] =
{
SIC (0, 0, "bfin_pll", "pll"),
-/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
- SIC (0, 1, "bfin_dmar@0", "block"),
- SIC (0, 1, "bfin_dmar@1", "block"),
- SIC (0, 1, "bfin_dmar@0", "overflow"),
- SIC (0, 1, "bfin_dmar@1", "overflow"),
- SIC (0, 2, "bfin_can@0", "stat"),
- SIC (0, 2, "bfin_emac", "stat"),
- SIC (0, 2, "bfin_sport@0", "stat"),
- SIC (0, 2, "bfin_sport@1", "stat"),
- SIC (0, 2, "bfin_ppi@0", "stat"),
- SIC (0, 2, "bfin_spi@0", "stat"),
- SIC (0, 2, "bfin_uart@0", "stat"),
- SIC (0, 2, "bfin_uart@1", "stat"),
+ SIC (0, 1, "glue-or@1", "int"),
+/*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/
+ PORT ("glue-or@1", "int", "bfin_dmar@0", "block"),
+ PORT ("glue-or@1", "int", "bfin_dmar@1", "block"),
+ PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"),
+ PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"),
+ SIC (0, 2, "glue-or@2", "int"),
+ PORT ("glue-or@2", "int", "bfin_can@0", "stat"),
+ PORT ("glue-or@2", "int", "bfin_emac", "stat"),
+ PORT ("glue-or@2", "int", "bfin_sport@0", "stat"),
+ PORT ("glue-or@2", "int", "bfin_sport@1", "stat"),
+ PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"),
+ PORT ("glue-or@2", "int", "bfin_spi@0", "stat"),
+ PORT ("glue-or@2", "int", "bfin_uart@0", "stat"),
+ PORT ("glue-or@2", "int", "bfin_uart@1", "stat"),
SIC (0, 3, "bfin_rtc", "rtc"),
SIC (0, 4, "bfin_dma@0", "di"),
SIC (0, 5, "bfin_dma@3", "di"),
SIC (0, 14, "bfin_dma@11", "di"),
SIC (0, 15, "bfin_can@0", "rx"),
SIC (0, 16, "bfin_can@0", "tx"),
- SIC (0, 17, "bfin_dma@1", "di"),
- SIC (0, 17, "bfin_gpio@7", "mask_a"),
- SIC (0, 18, "bfin_dma@2", "di"),
- SIC (0, 18, "bfin_gpio@7", "mask_b"),
+ SIC (0, 17, "glue-or@17", "int"),
+ PORT ("glue-or@17", "int", "bfin_dma@1", "di"),
+ PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"),
+ SIC (0, 18, "glue-or@18", "int"),
+ PORT ("glue-or@18", "int", "bfin_dma@2", "di"),
+ PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"),
SIC (0, 19, "bfin_gptimer@0", "stat"),
SIC (0, 20, "bfin_gptimer@1", "stat"),
SIC (0, 21, "bfin_gptimer@2", "stat"),
SIC (0, 24, "bfin_gptimer@5", "stat"),
SIC (0, 25, "bfin_gptimer@6", "stat"),
SIC (0, 26, "bfin_gptimer@7", "stat"),
- SIC (0, 27, "bfin_gpio@5", "mask_a"),
- SIC (0, 27, "bfin_gpio@6", "mask_a"),
+ SIC (0, 27, "glue-or@27", "int"),
+ PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"),
+ PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"),
SIC (0, 28, "bfin_gpio@6", "mask_b"),
SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
- SIC (0, 31, "bfin_wdog@0", "gpi"),
- SIC (0, 31, "bfin_gpio@5", "mask_b"),
+ SIC (0, 31, "glue-or@31", "int"),
+ PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"),
+ PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"),
};
#define bf534_port bf537_port
#define bf536_port bf537_port
{
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
_DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
+ DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
+ DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
+ DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
+ DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
+ DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
+ DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
+ DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
+ DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
+ DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
+ DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
+ DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
_DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
_DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
+ DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
+ DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
+ DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
+ DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
+ DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
+ DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
+ DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
+ DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
+ DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
+ DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
+ DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
_DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
_DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
+ DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
+ DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
+ DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
+ DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
+ DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
+ DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
+ DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
+ DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
+ DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
+ DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
+ DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
#define bf547_dmac bf54x_dmac
#define bf548_dmac bf54x_dmac
#define bf549_dmac bf54x_dmac
+#define PINT_PIQS(p, b, g) \
+ PORT (p, "piq0@"#b, g, "p0"), \
+ PORT (p, "piq1@"#b, g, "p1"), \
+ PORT (p, "piq2@"#b, g, "p2"), \
+ PORT (p, "piq3@"#b, g, "p3"), \
+ PORT (p, "piq4@"#b, g, "p4"), \
+ PORT (p, "piq5@"#b, g, "p5"), \
+ PORT (p, "piq6@"#b, g, "p6"), \
+ PORT (p, "piq7@"#b, g, "p7"), \
+ PORT (p, "piq8@"#b, g, "p8"), \
+ PORT (p, "piq9@"#b, g, "p9"), \
+ PORT (p, "piq10@"#b, g, "p10"), \
+ PORT (p, "piq11@"#b, g, "p11"), \
+ PORT (p, "piq12@"#b, g, "p12"), \
+ PORT (p, "piq13@"#b, g, "p13"), \
+ PORT (p, "piq14@"#b, g, "p14"), \
+ PORT (p, "piq15@"#b, g, "p15")
static const struct bfin_port_layout bf54x_port[] =
{
SIC (0, 0, "bfin_pll", "pll"),
SIC (0, 17, "bfin_gptimer@9", "stat"),
SIC (0, 18, "bfin_gptimer@10", "stat"),
SIC (0, 19, "bfin_pint@0", "stat"),
+ PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"),
+ PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"),
SIC (0, 20, "bfin_pint@1", "stat"),
+ PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"),
+ PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"),
SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
SIC (2, 28, "bfin_gptimer@6", "stat"),
SIC (2, 29, "bfin_gptimer@7", "stat"),
SIC (2, 30, "bfin_pint@2", "stat"),
+ PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"),
+ PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"),
+ PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"),
+ PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"),
+ PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"),
+ PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"),
+ PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"),
+ PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"),
SIC (2, 31, "bfin_pint@3", "stat"),
+ PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"),
+ PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"),
+ PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"),
+ PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"),
+ PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"),
+ PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"),
+ PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"),
+ PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"),
};
#define bf542_port bf54x_port
#define bf544_port bf54x_port
/* Map the system devices. */
dv_bfin_hw_parse (sd, sic, SIC);
- sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num);
for (i = 7; i < 16; ++i)
sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
{
const struct bfin_dev_layout *dev = &mdata->dev[i];
- sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
- sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
+ if (dev->len)
+ {
+ sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
+ sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
+ }
+ else
+ {
+ sim_hw_parse (sd, "/core/%s", dev->dev);
+ }
+
+ dv_bfin_hw_port_parse (sd, mdata, dev->dev);
if (strchr (dev->dev, '/'))
continue;
- dv_bfin_hw_port_parse (sd, mdata, dev->dev);
if (!strncmp (dev->dev, "bfin_uart", 9)
|| !strncmp (dev->dev, "bfin_emac", 9)
};
static const struct bfrom bf54x_roms[] =
{
- BFROM (54x, 4, 0),
- BFROM (54x, 2, 0),
- BFROM (54x, 1, 0),
- BFROM (54x, 0, 0),
- BFROMA (0xffa14000, 54x_l1, 4, 0),
- BFROMA (0xffa14000, 54x_l1, 2, 0),
- BFROMA (0xffa14000, 54x_l1, 1, 0),
- BFROMA (0xffa14000, 54x_l1, 0, 0),
+ BFROM (54x, 4, 0x1000),
+ BFROM (54x, 2, 0x1000),
+ BFROM (54x, 1, 0x1000),
+ BFROM (54x, 0, 0x1000),
+ BFROMA (0xffa14000, 54x_l1, 4, 0x10000),
+ BFROMA (0xffa14000, 54x_l1, 2, 0x10000),
+ BFROMA (0xffa14000, 54x_l1, 1, 0x10000),
+ BFROMA (0xffa14000, 54x_l1, 0, 0x10000),
BFROM_STUB,
};
static const struct bfrom bf561_roms[] =
{
/* XXX: No idea what the actual wrap limit is here. */
- BFROM (561, 5, 0),
+ BFROM (561, 5, 0x1000),
BFROM_STUB,
};
static const struct bfrom bf59x_roms[] =
{
BFROM (59x, 1, 0x1000000),
BFROM (59x, 0, 0x1000000),
- BFROMA (0xffa10000, 59x_l1, 1, 0),
+ BFROMA (0xffa10000, 59x_l1, 1, 0x10000),
BFROM_STUB,
};
else if (mnum >= 531 && mnum <= 533)
bfrom = bf533_roms;
else if (mnum == 535)
- /* Stub. */;
+ return; /* Stub. */
else if (mnum >= 534 && mnum <= 537)
bfrom = bf537_roms;
else if (mnum >= 538 && mnum <= 539)
else if (rn == SIM_BFIN_CC_REGNUM)
value = CCREG;
else
- return 0; // will be an error in gdb
+ return -1;
/* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
have the normal SP/USP behavior. User mode is tricky though. */
bfin_store_unsigned_integer (buf, 4, value);
- return -1; // disables size checking in gdb
+ return 4;
}
static int
else if (rn == SIM_BFIN_CC_REGNUM)
SET_CCREG (value);
else
- return 0; // will be an error in gdb
+ return -1;
- return -1; // disables size checking in gdb
+ return 4;
}
static sim_cia