$(CC) -c $(srccom)/sim-bits.c $(ALL_CFLAGS)
sim-config.o: $(srccom)/sim-config.c $(sim-config_h) \
- $(SIM_EXTRA_DEPS)
+ $(SIM_EXTRA_DEPS)
$(CC) -c $(srccom)/sim-config.c $(ALL_CFLAGS)
-sim-core.o: $(srccom)/sim-core.c $(sim-core_h) $(sim-n-core_h) \
+sim-core.o: $(srccom)/sim-core.c $(sim_main_headers) \
+ $(sim-core_h) $(sim-n-core_h) \
$(SIM_EXTRA_DEPS)
$(CC) -c $(srccom)/sim-core.c $(ALL_CFLAGS)
.gdbinit: # config.status $(srccom)/gdbinit.in
CONFIG_FILES=$@:../common/gdbinit.in CONFIG_HEADERS= $(SHELL) ./config.status
+# CGEN support
+
+SCHEME = @SCHEME@
+SCHEME = guile-ss
+SCHEME = guile
+#SCHEMEFLAGS = -b
+SCHEMEFLAGS = -s
+srccgen = $(srcroot)/cgen
+
+CGEN_VERBOSE = -v
+CGEN_MAIN_SCM = $(srccgen)/object.scm \
+ $(srccgen)/utils.scm $(srccgen)/utils-cgen.scm \
+ $(srccgen)/mode.scm \
+ $(srccgen)/cpu.scm $(srccgen)/mach.scm \
+ $(srccgen)/ifield.scm $(srccgen)/iformat.scm \
+ $(srccgen)/operand.scm $(srccgen)/insn.scm \
+ $(srccgen)/sim.scm
+CGEN_CPU_SCM = $(srccgen)/sim-cpu.scm $(srccgen)/sem-ccode.scm
+CGEN_DECODE_SCM = $(srccgen)/decode.scm
+
+# Various choices for which cpu specific files to generate.
+CGEN_CPU_EXTR = -E tmp-ext.c1
+CGEN_CPU_READ = -R tmp-read.c1
+CGEN_CPU_SEM = -S tmp-sem.c1
+CGEN_CPU_SEMSW = -W tmp-semsw.c1
+
+# We store the generated files in the source directory until we decide to
+# ship a Scheme interpreter with gdb/binutils. Maybe we never will.
+
+cgen-arch: force
+ $(SHELL) $(srccom)/cgen.sh arch $(srcdir) \
+ $(SCHEME) $(SCHEMEFLAGS) \
+ $(srccgen) $(CGEN_VERBOSE) \
+ $(arch) "$(FLAGS)" ignored ignored ignored ignored
+
+cgen-cpu: force
+ $(SHELL) $(srccom)/cgen.sh cpu $(srcdir) \
+ $(SCHEME) $(SCHEMEFLAGS) \
+ $(srccgen) $(CGEN_VERBOSE) \
+ $(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" "$(EXTRAFILES)"
+
+cgen-decode: force
+ $(SHELL) $(srccom)/cgen.sh decode $(srcdir) \
+ $(SCHEME) $(SCHEMEFLAGS) \
+ $(srccgen) $(CGEN_VERBOSE) \
+ $(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" ignored
+
## End COMMON_POST_CONFIG_FRAG