This commit was generated by cvs2svn to track changes on a CVS vendor

[deliverable/binutils-gdb.git] / sim / common / cgen-defs.h

diff --git a/sim/common/cgen-defs.h b/sim/common/cgen-defs.h
index d3c9a8ae57baddea2e8b2bd974756d914d29b191..fbdfb9a279164478a5cc21157075b328fa7b9e7c 100644 (file)
--- a/sim/common/cgen-defs.h
+++ b/sim/common/cgen-defs.h
@@ -92,6 +92,15 @@ typedef SCACHE *SEM_PC;
 #else
 typedef IADDR SEM_PC;
 #endif
+
+/* Kinds of branches.  */
+typedef enum {
+  SEM_BRANCH_UNTAKEN,
+  /* Branch to an uncacheable address (e.g. j reg).  */
+  SEM_BRANCH_UNCACHEABLE,
+  /* Branch to a cacheable (fixed) address.  */
+  SEM_BRANCH_CACHEABLE
+} SEM_BRANCH_TYPE;
 \f
 /* Virtual insn support.  */
 
@@ -106,7 +115,7 @@ typedef enum {
   VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5
 } CGEN_INSN_VIRTUAL_TYPE;
 
-/* Return non-zero if OPCODE is a virtual insn.  */
+/* Return non-zero if CGEN_INSN* INSN is a virtual insn.  */
 #define CGEN_INSN_VIRTUAL_P(insn) \
   CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL)
 \f
@@ -168,7 +177,7 @@ extern CPU_INSN_NAME_FN cgen_insn_name;
    language [or suggest a better way].  */
 extern int cgen_cpu_max_extra_bytes (void);
 
-/* Called to process an invalid instruction.  */
-extern void sim_engine_invalid_insn (SIM_CPU *, IADDR);
+/* Target supplied routine to process an invalid instruction.  */
+extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC);
 
 #endif /* CGEN_DEFS_H */