-/* This file is part of the program psim.
+/* The common simulator framework for GDB, the GNU Debugger.
- Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+ Copyright 2002-2020 Free Software Foundation, Inc.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
+ Contributed by Andrew Cagney and Red Hat.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- */
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef SIM_CORE_H
void *free_buffer;
void *buffer;
/* callback map */
-#if (WITH_HW)
struct hw *device;
-#else
- device *device;
-#endif
/* tracing */
int trace;
/* growth */
typedef struct _sim_cpu_core {
sim_core_common common;
- address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
+ address_word byte_xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
} sim_cpu_core;
translated into ADDRESS_SPACE:OFFSET before being passed to the
client device.
- MODULO - when the simulator has been configured WITH_MODULO support
- and is greater than zero, specifies that accesses to the region
- [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
- .. ADDR+MODULO). The modulo value must be a power of two.
+ MODULO - Specifies that accesses to the region [ADDR .. ADDR+NR_BYTES)
+ should be mapped onto the sub region [ADDR .. ADDR+MODULO). The modulo
+ value must be a power of two.
DEVICE - When non NULL, indicates that this is a callback memory
space and specified device's memory callback handler should be
address_word addr,
address_word nr_bytes,
unsigned modulo,
-#if (WITH_HW)
struct hw *client,
-#else
- device *client,
-#endif
void *optional_buffer);
/* Variable sized read/write
Transfer a variable sized block of raw data between the host and
- target. Should any problems occure, the number of bytes
+ target. Should any problems occur, the number of bytes
successfully transfered is returned.
No host/target byte endian conversion is performed. No xor-endian
/* XOR version of variable sized read/write.
Transfer a variable sized block of raw data between the host and
- target. Should any problems occure, the number of bytes
+ target. Should any problems occur, the number of bytes
successfully transfered is returned.
No host/target byte endian conversion is performed. If applicable
unsigned nr_bytes);
+/* Translate an address based on a map. */
+
+extern void *sim_core_trans_addr
+(SIM_DESC sd,
+ sim_cpu *cpu,
+ unsigned map,
+ address_word addr);
+
/* Fixed sized, processor oriented, read/write.
DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
-#define sim_core_write_unaligned_1 sim_core_write_aligned_1
+#define sim_core_write_unaligned_1 sim_core_write_aligned_1
DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
#undef DECLARE_SIM_CORE_READ_N
-
#endif