Regenerate configure in sim

[deliverable/binutils-gdb.git] / sim / cris / Makefile.in

diff --git a/sim/cris/Makefile.in b/sim/cris/Makefile.in
index 85af034c218115c44c8e2d615ef74e50b53dfe5d..0b444011f1127f4bcb2f165ff6d52c41c9656e27 100644 (file)
--- a/sim/cris/Makefile.in
+++ b/sim/cris/Makefile.in
@@ -1,12 +1,12 @@
 # Makefile template for Configure for the CRIS simulator, based on a mix
 # of the ones for m32r and i960.
 #
-# Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+# Copyright (C) 2004-2015 Free Software Foundation, Inc.
 # Contributed by Axis Communications.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
@@ -14,22 +14,17 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 ## COMMON_PRE_CONFIG_FRAG
 
-CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o semcrisv10f-switch.o modelv10.o mloopv10f.o
-CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o semcrisv32f-switch.o modelv32.o mloopv32f.o
-
-CONFIG_DEVICES = dv-sockser.o
-CONFIG_DEVICES =
+CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o modelv10.o mloopv10f.o
+CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o modelv32.o mloopv32f.o
 
 SIM_OBJS = \
        $(SIM_NEW_COMMON_OBJS) \
        sim-cpu.o \
-       sim-hload.o \
        sim-hrw.o \
        sim-model.o \
        sim-reg.o \
@@ -39,7 +34,6 @@ SIM_OBJS = \
        $(CRISV10F_OBJS) \
        $(CRISV32F_OBJS) \
        traps.o devices.o \
-       $(CONFIG_DEVICES) \
        cris-desc.o
 
 # Extra headers included by sim-main.h.
@@ -48,7 +42,6 @@ SIM_EXTRA_DEPS = \
        $(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \
        arch.h cpuall.h cris-sim.h cris-desc.h
 
-SIM_RUN_OBJS = nrun.o
 SIM_EXTRA_CLEAN = cris-clean
 
 # This selects the cris newlib/libgloss syscall definitions.
@@ -62,11 +55,29 @@ arch = cris
 
 sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(sim-core_h) $(sim-options_h)
 
+# Needs CPU-specific knowledge.
+dv-cris.o: dv-cris.c $(SIM_MAIN_DEPS) $(sim-core_h)
+
+# This is the same rule as dv-core.o etc.
+dv-rv.o: dv-rv.c $(hw_main_headers) $(sim_main_headers)
+
 arch.o: arch.c $(SIM_MAIN_DEPS)
 
 traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS) $(sim-options_h)
 devices.o: devices.c $(SIM_MAIN_DEPS)
 
+# rvdummy is just used for testing.  It does nothing if
+# --enable-sim-hardware isn't active.
+
+all: rvdummy$(EXEEXT)
+
+check: rvdummy$(EXEEXT)
+
+rvdummy$(EXEEXT): rvdummy.o $(EXTRA_LIBDEPS)
+       $(CC) $(ALL_CFLAGS) -o rvdummy$(EXEEXT) rvdummy.o $(EXTRA_LIBS)
+
+rvdummy.o: rvdummy.c config.h tconfig.h $(remote_sim_h) $(callback_h)
+
 # CRISV10 objs
 
 CRISV10F_INCLUDE_DEPS = \
@@ -79,7 +90,7 @@ crisv10f.o: crisv10f.c cris-tmpl.c $(CRISV10F_INCLUDE_DEPS)
 # than the apparent; some "mono" feature is work in progress)?
 mloopv10f.c engv10.h: stamp-v10fmloop
 stamp-v10fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
-       $(SHELL) $(srccom)/genmloop.sh \
+       $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
                -mono -no-fast -pbb -switch semcrisv10f-switch.c \
                -cpu crisv10f -infile $(srcdir)/mloop.in
        $(SHELL) $(srcroot)/move-if-change eng.hin engv10.h
@@ -89,7 +100,6 @@ mloopv10f.o: mloopv10f.c semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
 
 cpuv10.o: cpuv10.c $(CRISV10F_INCLUDE_DEPS)
 decodev10.o: decodev10.c $(CRISV10F_INCLUDE_DEPS)
-semcrisv10f-switch.o: semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
 modelv10.o: modelv10.c $(CRISV10F_INCLUDE_DEPS)
 
 # CRISV32 objs
@@ -106,7 +116,7 @@ mloopv32f.c engv32.h: stamp-v32fmloop
 # We depend on stamp-v10fmloop to get serialization to avoid
 # racing with it for the same temporary file-names when "make -j".
 stamp-v32fmloop: stamp-v10fmloop $(srcdir)/../common/genmloop.sh mloop.in Makefile
-       $(SHELL) $(srccom)/genmloop.sh \
+       $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
                -mono -no-fast -pbb -switch semcrisv32f-switch.c \
                -cpu crisv32f -infile $(srcdir)/mloop.in
        $(SHELL) $(srcroot)/move-if-change eng.hin engv32.h
@@ -116,7 +126,6 @@ mloopv32f.o: mloopv32f.c semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
 
 cpuv32.o: cpuv32.c $(CRISV32F_INCLUDE_DEPS)
 decodev32.o: decodev32.c $(CRISV32F_INCLUDE_DEPS)
-semcrisv32f-switch.o: semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
 modelv32.o: modelv32.c $(CRISV32F_INCLUDE_DEPS)
 
 cris-clean: