THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/* The hardware table. */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
-#else
-#define A(a) (1 << CGEN_HW_/**/a)
-#endif
const CGEN_HW_ENTRY cris_cgen_hw_table[] =
{
/* The instruction field table. */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
-#else
-#define A(a) (1 << CGEN_IFLD_/**/a)
-#endif
const CGEN_IFLD cris_cgen_ifld_table[] =
{
/* The operand table. */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
-#else
-#define A(a) (1 << CGEN_OPERAND_/**/a)
-#endif
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) CRIS_OPERAND_##op
-#else
-#define OPERAND(op) CRIS_OPERAND_/**/op
-#endif
const CGEN_OPERAND cris_cgen_operand_table[] =
{
/* The instruction table. */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
-#else
-#define A(a) (1 << CGEN_INSN_/**/a)
-#endif
static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] =
{
CRIS_INSN_MOVE_M_SPRV32, "move-m-sprv32", "move", 16,
{ 0, { { { (1<<MACH_CRISV32), 0 } } } }
},
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV0_P0, "move-c-sprv0-p0", "move", 32,
- { 0, { { { (1<<MACH_CRISV0), 0 } } } }
- },
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV0_P1, "move-c-sprv0-p1", "move", 32,
- { 0, { { { (1<<MACH_CRISV0), 0 } } } }
- },
-/* move ${sconst16},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV0_P4, "move-c-sprv0-p4", "move", 32,
- { 0, { { { (1<<MACH_CRISV0), 0 } } } }
- },
/* move ${sconst16},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV0_P5, "move-c-sprv0-p5", "move", 32,
{ 0, { { { (1<<MACH_CRISV0), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV0_P8, "move-c-sprv0-p8", "move", 48,
- { 0, { { { (1<<MACH_CRISV0), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV0_P9, "move-c-sprv0-p9", "move", 48,
CRIS_INSN_MOVE_C_SPRV0_P7, "move-c-sprv0-p7", "move", 32,
{ 0, { { { (1<<MACH_CRISV0), 0 } } } }
},
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV3_P0, "move-c-sprv3-p0", "move", 32,
- { 0, { { { (1<<MACH_CRISV3), 0 } } } }
- },
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV3_P1, "move-c-sprv3-p1", "move", 32,
- { 0, { { { (1<<MACH_CRISV3), 0 } } } }
- },
-/* move ${sconst16},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV3_P4, "move-c-sprv3-p4", "move", 32,
- { 0, { { { (1<<MACH_CRISV3), 0 } } } }
- },
/* move ${sconst16},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV3_P5, "move-c-sprv3-p5", "move", 32,
{ 0, { { { (1<<MACH_CRISV3), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV3_P8, "move-c-sprv3-p8", "move", 48,
- { 0, { { { (1<<MACH_CRISV3), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV3_P9, "move-c-sprv3-p9", "move", 48,
CRIS_INSN_MOVE_C_SPRV3_P14, "move-c-sprv3-p14", "move", 48,
{ 0, { { { (1<<MACH_CRISV3), 0 } } } }
},
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV8_P0, "move-c-sprv8-p0", "move", 32,
- { 0, { { { (1<<MACH_CRISV8), 0 } } } }
- },
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV8_P1, "move-c-sprv8-p1", "move", 32,
- { 0, { { { (1<<MACH_CRISV8), 0 } } } }
- },
-/* move ${sconst16},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV8_P4, "move-c-sprv8-p4", "move", 32,
- { 0, { { { (1<<MACH_CRISV8), 0 } } } }
- },
/* move ${sconst16},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV8_P5, "move-c-sprv8-p5", "move", 32,
{ 0, { { { (1<<MACH_CRISV8), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV8_P8, "move-c-sprv8-p8", "move", 48,
- { 0, { { { (1<<MACH_CRISV8), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV8_P9, "move-c-sprv8-p9", "move", 48,
CRIS_INSN_MOVE_C_SPRV8_P14, "move-c-sprv8-p14", "move", 48,
{ 0, { { { (1<<MACH_CRISV8), 0 } } } }
},
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV10_P0, "move-c-sprv10-p0", "move", 32,
- { 0, { { { (1<<MACH_CRISV10), 0 } } } }
- },
-/* move ${sconst8},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV10_P1, "move-c-sprv10-p1", "move", 32,
- { 0, { { { (1<<MACH_CRISV10), 0 } } } }
- },
-/* move ${sconst16},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV10_P4, "move-c-sprv10-p4", "move", 32,
- { 0, { { { (1<<MACH_CRISV10), 0 } } } }
- },
/* move ${sconst16},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV10_P5, "move-c-sprv10-p5", "move", 32,
{ 0, { { { (1<<MACH_CRISV10), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV10_P8, "move-c-sprv10-p8", "move", 48,
- { 0, { { { (1<<MACH_CRISV10), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV10_P9, "move-c-sprv10-p9", "move", 48,
CRIS_INSN_MOVE_C_SPRV10_P15, "move-c-sprv10-p15", "move", 48,
{ 0, { { { (1<<MACH_CRISV10), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV32_P0, "move-c-sprv32-p0", "move", 48,
- { 0, { { { (1<<MACH_CRISV32), 0 } } } }
- },
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV32_P1, "move-c-sprv32-p1", "move", 48,
- { 0, { { { (1<<MACH_CRISV32), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV32_P2, "move-c-sprv32-p2", "move", 48,
CRIS_INSN_MOVE_C_SPRV32_P3, "move-c-sprv32-p3", "move", 48,
{ 0, { { { (1<<MACH_CRISV32), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV32_P4, "move-c-sprv32-p4", "move", 48,
- { 0, { { { (1<<MACH_CRISV32), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV32_P5, "move-c-sprv32-p5", "move", 48,
CRIS_INSN_MOVE_C_SPRV32_P7, "move-c-sprv32-p7", "move", 48,
{ 0, { { { (1<<MACH_CRISV32), 0 } } } }
},
-/* move ${const32},${Pd} */
- {
- CRIS_INSN_MOVE_C_SPRV32_P8, "move-c-sprv32-p8", "move", 48,
- { 0, { { { (1<<MACH_CRISV32), 0 } } } }
- },
/* move ${const32},${Pd} */
{
CRIS_INSN_MOVE_C_SPRV32_P9, "move-c-sprv32-p9", "move", 48,
CRIS_INSN_BDAPQPC, "bdapqpc", "bdapq", 16,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
},
+/* bdap ${sconst32},PC */
+ {
+ CRIS_INSN_BDAP_32_PC, "bdap-32-pc", "bdap", 48,
+ { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
+ },
+/* move [PC+],P0 */
+ {
+ CRIS_INSN_MOVE_M_PCPLUS_P0, "move-m-pcplus-p0", "move", 16,
+ { 0|A(COND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
+ },
+/* move [SP+],P8 */
+ {
+ CRIS_INSN_MOVE_M_SPPLUS_P8, "move-m-spplus-p8", "move", 16,
+ { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
+ },
/* addo-m.b [${Rs}${inc}],$Rd,ACR */
{
CRIS_INSN_ADDO_M_B_M, "addo-m.b-m", "addo-m.b", 16,
CGEN_CPU_OPEN_END: terminates arguments
??? Simultaneous multiple isas might not make sense, but it's not (yet)
- precluded.
-
- ??? We only support ISO C stdargs here, not K&R.
- Laziness, plus experiment to see if anything requires K&R - eventually
- K&R will no longer be supported - e.g. GDB is currently trying this. */
+ precluded. */
CGEN_CPU_DESC
cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
projects / deliverable / binutils-gdb.git / blobdiff