#include "ansidecl.h"
#include "callback.h"
#include "opcode/d10v.h"
+#include "bfd.h"
#define DEBUG_TRACE 0x00000001
#define DEBUG_VALUES 0x00000002
-#define DEBUG_MEMSIZE 0x00000004
-#define DEBUG_INSTRUCTION 0x00000008
+#define DEBUG_LINE_NUMBER 0x00000004
+#define DEBUG_MEMSIZE 0x00000008
+#define DEBUG_INSTRUCTION 0x00000010
+
+#ifndef DEBUG
+#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
+#endif
extern int d10v_debug;
enum _ins_type
{
- INS_UNKNOWN,
- INS_LEFT,
- INS_RIGHT,
- INS_LEFT_PARALLEL,
- INS_RIGHT_PARALLEL,
- INS_LONG,
+ INS_UNKNOWN, /* unknown instruction */
+ INS_COND_TRUE, /* # times EXExxx executed other instruction */
+ INS_COND_FALSE, /* # times EXExxx did not execute other instruction */
+ INS_COND_JUMP, /* # times JUMP skipped other instruction */
+ INS_CYCLES, /* # cycles */
+ INS_LONG, /* long instruction (both containers, ie FM == 11) */
+ INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */
+ INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */
+ INS_PARALLEL, /* # times instruction encoded as L || R (ie, RM == 00) */
+
+ INS_LEFT, /* normal left instructions */
+ INS_LEFT_PARALLEL, /* left side of || */
+ INS_LEFT_COND_TEST, /* EXExx test on left side */
+ INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */
+ INS_LEFT_NOPS, /* NOP on left side */
+
+ INS_RIGHT, /* normal right instructions */
+ INS_RIGHT_PARALLEL, /* right side of || */
+ INS_RIGHT_COND_TEST, /* EXExx test on right side */
+ INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */
+ INS_RIGHT_NOPS, /* NOP on right side */
+
INS_MAX
};
-extern long ins_type_counters[ (int)INS_MAX ];
-extern long left_nops, right_nops;
+extern unsigned long ins_type_counters[ (int)INS_MAX ];
struct _state
{
reg_t regs[16]; /* general-purpose registers */
- reg_t cregs[16]; /* control registers */
- int64 a[2]; /* accumulators */
+ reg_t cregs[16]; /* control registers */
+ int64 a[2]; /* accumulators */
uint8 SM;
uint8 EA;
uint8 DB;
uint8 F1;
uint8 C;
uint8 exe;
+ int exception;
+ /* everything below this line is not reset by sim_create_inferior() */
uint8 *imem;
uint8 *dmem;
- int exception;
+ uint8 *umem[128];
enum _ins_type ins_type;
} State;
extern host_callback *d10v_callback;
extern uint16 OP[4];
extern struct simops Simops[];
+extern asection *text;
+extern bfd_vma text_start;
+extern bfd_vma text_end;
+extern bfd *exec_bfd;
#define PC (State.cregs[2])
#define PSW (State.cregs[0])
#define MOD_E (State.cregs[11])
#define IBA (State.cregs[14])
+#define SIG_D10V_STOP -1
+#define SIG_D10V_EXIT -2
+
#define SEXT3(x) ((((x)&0x7)^(~3))+4)
/* sign-extend a 4-bit number */
#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
-#define RB(x) (*((uint8 *)((x)+State.imem)))
-#define SB(addr,data) ( RB(addr) = (data & 0xff))
+extern uint8 *dmem_addr PARAMS ((uint32));
+extern bfd_vma decode_pc PARAMS ((void));
-#ifdef WORDS_BIGENDIAN
+#define RB(x) (*(dmem_addr(x)))
+#define SB(addr,data) ( RB(addr) = (data & 0xff))
-#define RW(x) (*((uint16 *)((x)+State.imem)))
-#define RLW(x) (*((uint32 *)((x)+State.imem)))
-#define SW(addr,data) RW(addr)=data
-#define SLW(addr,data) RLW(addr)=data
-#define READ_16(x) (*((int16 *)(x)))
-#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
-#define READ_64(x) (*((int64 *)(x)))
-#define WRITE_64(addr,data) (*(int64 *)(addr)=data)
+#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
+#define ENDIAN_INLINE static __inline__
+#include "endian.c"
+#undef ENDIAN_INLINE
#else
+extern uint32 get_longword PARAMS ((uint8 *));
+extern uint16 get_word PARAMS ((uint8 *));
+extern int64 get_longlong PARAMS ((uint8 *));
+extern void write_word PARAMS ((uint8 *addr, uint16 data));
+extern void write_longword PARAMS ((uint8 *addr, uint32 data));
+extern void write_longlong PARAMS ((uint8 *addr, int64 data));
+#endif
-uint32 get_longword PARAMS ((uint8 *));
-uint16 get_word PARAMS ((uint8 *));
-int64 get_longlong PARAMS ((uint8 *));
-void write_word PARAMS ((uint8 *addr, uint16 data));
-void write_longword PARAMS ((uint8 *addr, uint32 data));
-void write_longlong PARAMS ((uint8 *addr, int64 data));
-
-#define SW(addr,data) write_word((long)(addr)+State.imem,data)
-#define RW(x) get_word((long)(x)+State.imem)
-#define SLW(addr,data) write_longword((long)(addr)+State.imem,data)
-#define RLW(x) get_longword((long)(x)+State.imem)
+#define SW(addr,data) write_word(dmem_addr(addr),data)
+#define RW(x) get_word(dmem_addr(x))
+#define SLW(addr,data) write_longword(dmem_addr(addr),data)
+#define RLW(x) get_longword(dmem_addr(x))
#define READ_16(x) get_word(x)
#define WRITE_16(addr,data) write_word(addr,data)
#define READ_64(x) get_longlong(x)
#define WRITE_64(addr,data) write_longlong(addr,data)
-#endif /* not WORDS_BIGENDIAN */
+#define IMAP0 RW(0xff00)
+#define IMAP1 RW(0xff02)
+#define DMAP RW(0xff04)
+#define SET_IMAP0(x) SW(0xff00,x)
+#define SET_IMAP1(x) SW(0xff02,x)
+#define SET_DMAP(x) SW(0xff04,x)
projects / deliverable / binutils-gdb.git / blobdiff